Resistive random-access memory

Resistive random-access memory (ReRAM or RRAM) is a type of non-volatile (NV) random-access (RAM) computer memory that works by changing the resistance across a dielectric solid-state material, often referred to as a memristor. This technology bears some similarities to conductive-bridging RAM (CBRAM), and phase-change memory (PCM).

CBRAM involves one electrode providing ions that dissolve readily in an electrolyte material, while PCM involves generating sufficient Joule heating to effect amorphous-to-crystalline or crystalline-to-amorphous phase changes. On the other hand, ReRAM involves generating defects in a thin oxide layer, known as oxygen vacancies (oxide bond locations where the oxygen has been removed), which can subsequently charge and drift under an electric field. The motion of oxygen ions and vacancies in the oxide would be analogous to the motion of electrons and holes in a semiconductor.

Although ReRAM was initially seen as a replacement technology for flash memory, the cost and performance benefits of ReRAM have not been enough for companies to proceed with the replacement. Apparently, a broad range of materials can be used for ReRAM. However, the discovery[1] that the popular high-κ gate dielectric HfO2 can be used as a low-voltage ReRAM has encouraged researchers to investigate more possibilities. Among these, SiOx has been found to offer significant benefits and is currently being explored by some companies such as Weebit-Nano Ltd.

RRAM® is the registered trademark name of Sharp Corporation, one of Japanese electronic components manufacturer, in some countries including EU.[2]


In the early 2000s, ReRAM was under development by a number of companies, some of which filed patent applications claiming various implementations of this technology.[3][4][5] ReRAM has entered commercialization on an initially limited KB-capacity scale.[6]

In February 2012, Rambus bought a ReRAM company called Unity Semiconductor for $35 million.[7] Panasonic launched an ReRAM evaluation kit in May 2012, based on a tantalum oxide 1T1R (1 transistor – 1 resistor) memory cell architecture.[8]

In 2013, Crossbar introduced an ReRAM prototype as a chip about the size of a postage stamp that could store 1 TB of data. In August 2013, the company claimed that large-scale production of their ReRAM chips was scheduled for 2015.[9] The memory structure (Ag/a-Si/Si) closely resembles a silver-based CBRAM.

Different forms of ReRAM have been disclosed, based on different dielectric materials, spanning from perovskites to transition metal oxides to chalcogenides. Silicon dioxide was shown to exhibit resistive switching as early as May 1966,[10] and has recently been revisited.[11][12]

In 1963 and 1964, a thin-film resistive memory array was first proposed by members of University of Nebraska–Lincoln.[13][14] Since August 1967, this new thin-film resistive memory has been presented by J.G. Simmons.[15][16] In 1970, member of Atomic Energy Research Establishment and University of Leeds tried to explain the mechanism theoretically.[17]:1180 In May 1997, a research team of University of Florida and Honeywell reported a manufacturing method for "magneto-resistive random access memory" by utilizing electron cyclotron resonance plasma etching.[18]

Leon Chua argued that all two-terminal non-volatile memory devices including ReRAM should be considered memristors.[19] Stan Williams of HP Labs also argued that ReRAM was a memristor.[20] However, others challenged this terminology and the applicability of memristor theory to any physically realizable device is open to question.[21][22] Whether redox-based resistively switching elements (ReRAM) are covered by the current memristor theory is disputed.[23]

Silicon oxide presents an interesting case of resistance switching. Two distinct modes of intrinsic switching have been reported - surface-based, in which conductive silicon filaments are generated at exposed edges (which may be internal - within pores - or external - on the surface of mesa structures), and bulk switching, in which oxygen vacancy filaments are generated within the bulk of the oxide. The former mode suffers from oxidation of the filaments in air, requiring hermetic sealing to enable switching. The latter requires no sealing. In 2014 researchers from Rice University announced a silicon filament-based device that used a porous silicon oxide dielectric with no external edge structure - rather, filaments were formed at internal edges within pores. Devices can be manufactured at room temperature and have a sub-2V forming voltage, high on-off ratio, low power consumption, nine-bit capacity per cell, high switching speeds and good endurance. Problems with their inoperability in air can be overcome by hermetic sealing of devices.[24] Bulk switching in silicon oxide, pioneered by researchers at UCL (University College London) since 2012,[12] offers low electroforming voltages (2.5V), switching voltages around 1V, switching times in the nanoseconds regime, and more than 10,000,000 cycles without device failure - all in ambient conditions.[25]


I-V of filamentary RRAM
Filament forming: A 50 nm × 50 nm ReRAM cell by Crossbar shows the instance of filament forming when the current abruptly increases beyond a certain voltage. A transistor is often used to limit current to prevent a runaway breakdown following the filament formation.

The basic idea is that a dielectric, which is normally insulating, can be made to conduct through a filament or conduction path formed after application of a sufficiently high voltage.[26] The conduction path can arise from different mechanisms, including vacancy or metal defect migration. Once the filament is formed, it may be reset (broken, resulting in high resistance) or set (re-formed, resulting in lower resistance) by another voltage. Many current paths, rather than a single filament, are possibly involved.[27] The presence of these current paths in the dielectric can be in situ demonstrated via conductive atomic force microscopy.[26][28][29][30]

The low-resistance path can be either localized (filamentary) or homogeneous. Both effects can occur either throughout the entire distance between the electrodes or only in proximity to one of the electrodes. Filamentary and homogenous switching effects can be distinguished by measuring the area dependence of the low-resistance state.[31]

Under certain conditions, the forming operation may be bypassed.[32] It is expected that under these conditions, the initial current is already quite high compared to insulating oxide layers.

CBRAM cells generally would not require forming if Cu ions are already present in the electrolyte, having already been driven-in by a designed photo-diffusion or annealing process; such cells may also readily return to their initial state.[33] In the absence of such Cu initially being in the electrolyte, the voltage would still be applied directly to the electrolyte, and forming would be a strong possibility.[34]

Operation styles

For random-access type memories, a 1T1R (one transistor, one resistor) architecture is preferred because the transistor isolates current to cells that are selected from cells that are not. On the other hand, a cross-point architecture is more compact and may enable vertically stacking memory layers, ideally suited for mass-storage devices. However, in the absence of any transistors, isolation must be provided by a "selector" device, such as a diode, in series with the memory element or by the memory element itself. Such isolation capabilities are inferior to the use of transistors if the on/off ratio for the selector is not sufficient, limiting the ability to operate very large arrays in this architecture. Thin film based threshold switch can work as a selector for bipolar and unipolar ReRAM. Threshold switch-based selector was demonstrated for 64 Mb array.[35] The cross-point architecture requires BEOL compatible two terminal selectors like punch-through diode for bipolar ReRAM[36] or PIN diode for unipolar ReRAM.[37]

Polarity can be either binary or unary. Bipolar effects cause polarity to reverse when switching from low to high resistance (reset operation) compared to switching high to low (set operation). Unipolar switching leaves polarity unaffected, but uses different voltages.

Material systems for resistive memory cells

Multiple inorganic and organic material systems display thermal or ionic resistive switching effects. These can be grouped into the following categories:[31]

  • phase-change chalcogenides such as Ge
    or AgInSbTe
  • binary transition metal oxides such as NiO or TiO
  • perovskites such as Sr(Zr)TiO
    [38] or PCMO
  • solid-state electrolytes such as GeS, GeSe, SiO
    or Cu
  • organic charge-transfer complexes such as CuTCNQ
  • organic donor–acceptor systems such as Al AIDCN
  • two dimensional (layered) insulating materials like hexagonal boron nitride[39][40]


Papers at the IEDM Conference in 2007 suggested for the first time that ReRAM exhibits lower programming currents than PRAM or MRAM without sacrificing programming performance, retention or endurance.[41] Some commonly cited ReRAM systems are described further below.

HfO2-based ReRAM

At IEDM 2008, the highest-performance ReRAM technology to date was demonstrated by ITRI using HfO2 with a Ti buffer layer, showing switching times less than 10 ns and currents less than 30μA. At IEDM 2010, ITRI again broke the speed record, showing <0.3 ns switching time, while also showing process and operation improvements to allow yield up to 100% and endurance up to 10 billion cycles.[42] IMEC presented updates of their ReRAM program at the 2012 Symposia on VLSI Technology and Circuits, including a solution with a 500 nA operating current.[43]

ITRI had focused on the Ti/HfO2 system since its first publication in 2008. ITRI's patent 8362454 has since been sold to TSMC;[44] the number of prior licensees is unknown. On the other hand, IMEC focused mainly on Hf/HfO2.[45] Winbond had done more recent work toward advancing and commercializing the HfO2-based ReRAM.[46]


Panasonic revealed its TaOx-based ReRAM at IEDM 2008.[47] A key requirement was the need for a high work function metal such as Pt or Ir to interface with the TaOx layer. The change of O content results in resistance change as well as Schottky barrier change. More recently, a Ta2O5/TaOx layer was implemented, which still requires the high work function metal to interface with Ta2O5.[48] This system has been associated with high endurance demonstration (trillion cycles),[49] but products are specified at 100K cycles.[50] Filament diameters as large as ~100 nm have been observed.[51] Panasonic released a 4Mb part with Fujitsu,[52] and is developing 40 nm embedded memory with UMC.[53]

HP Memristor

On 30 April 2008, HP announced that they had discovered the memristor, originally envisioned as a missing 4th fundamental circuit element by Chua in 1971. On 8 July they announced they would begin prototyping ReRAM using their memristors.[54] HP first demonstrated its memristor using TiOx,[55] but later migrated to TaOx,[56] possibly due to improved stability.[57] The TaOx-based device has some material similarity to Panasonic's ReRAM, but the operation characteristics are different. The Hf/HfOx system was similarly studied.[58]

Adesto Technologies

The Adesto Technologies ReRAM is based on filaments generated from the electrode metal rather than oxygen vacancies. The original material system was Ag/GeS2[59] but eventually migrated to ZrTe/Al2O3.[60] The tellurium filament achieved better stability as compared to silver. Adesto has targeted the ultralow power memory for Internet-of-Things (IoT) applications. Adesto has released products manufactured at Altis foundry[61] and entered into a 45 nm foundry agreement with TowerJazz/Panasonic.[62]


Crossbar implements an Ag filament in amorphous Si along with a threshold switching system to achieve a diode+ReRAM.[63][64] Their system includes the use of a transistor in 1T1R or 1TNR architecture. Crossbar started producing samples at SMIC on the 40 nm process in 2017.[65] The Ag filament diameter has been visualized on the scale of tens of nanometers.[66]

Programmable metallization cell

Infineon Technologies calls it conductive-bridging RAM(CBRAM), NEC has a variant called “Nanobridge” and Sony calls their version “electrolytic memory”. New research suggests CBRAM can be 3D printed[67][68]

ReRam test boards

  • Panasonic AM13L-STK2 : MN101LR05D 8-bit MCU with built in ReRAM for evaluation, USB 2.0 connector

Future applications

Compared to PRAM, ReRAM operates at a faster timescale (switching time can be less than 10 ns), while compared to MRAM, it has a simpler, smaller cell structure (less than 8F² MIM stack). A vertical 1D1R (one diode, one resistive switching device) integration can be used for crossbar memory structure to reduce the unit cell size to 4F² (F is the feature dimension).[69] Compared to flash memory and racetrack memory, a lower voltage is sufficient, and hence it can be used in low-power applications. Also, due to its relatively small access latency and high density, ReRAM is considered a promising candidate for designing caches.[70]

ITRI has shown that ReRAM is scalable below 30 nm.[71] The motion of oxygen atoms is a key phenomenon for oxide-based ReRAM;[72] one study indicated that oxygen motion may take place in regions as small as 2 nm.[73] It is believed that if a filament is responsible, it would not exhibit direct scaling with cell size.[74] Instead, the current compliance limit (set by an outside resistor, for example) could define the current-carrying capacity of the filament.[75]

A significant hurdle to realizing the potential of ReRAM is the sneak path problem that occurs in larger passive arrays. In 2010, complementary resistive switching (CRS) was introduced as a possible solution to sneak-path current interference.[76] In the CRS approach, the information storing states are pairs of high- and low-resistance states (HRS/LRS and LRS/HRS) so that the overall resistance is always high, allowing larger passive crossbar arrays.

A drawback to the initial CRS solution is the requirement for switching endurance caused by conventional destructive readout based on current measurements. A new approach for a nondestructive readout based on capacity measurement potentially lowers the requirements for both material endurance and power consumption.[77] Bi-layer structure is used to produce the nonlinearity in LRS to avoid the sneak path problem.[78] A single-layer device exhibiting a strong nonlinear conduction in LRS was reported.[79] Another bi-layer structure was introduced for bipolar ReRAM to improve the HRS and stability.[80]

Another solution to the sneak current issue is to perform read and reset operations in parallel across an entire row of cells, while using set on selected cells.[81] In this case, for a 3D-ReRAM 1TNR array, with a column of N ReRAM cells situated above a select transistor, only the intrinsic nonlinearity of the HRS is required to be sufficiently large, since the number of vertical levels N is limited (e.g., N = 8–32), and this has been shown possible for a low-current ReRAM system.[82]

Modeling of 2D and 3D caches designed with ReRAM and other non-volatile random access memories such as MRAM and PCM can be done using DESTINY[83] tool.


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3D XPoint

3D XPoint (pronounced three dee cross point) is a non-volatile memory (NVM) technology developed jointly by Intel and Micron Technology. It was announced in July 2015 and is available on the open market under brand names Optane (Intel) and subsequently QuantX (Micron) since April 2017. Bit storage is based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Initial prices are less than dynamic random-access memory (DRAM) but more than flash memory.As a non-volatile memory, 3DXPoint has a number of features that distinguish it from other currently available RAM and NVRAM. Although the first generations of 3D XPoint were not especially large or fast, as of 2019 3D XPoint is used to create some of the fastest SSDs available, with small-write latency (the hardest type of task for most SSDs, sometimes described as "worst case" or "murderously" hard) being an order of magnitude faster than any preceding enterprise SSD. As the memory is inherently fast, and byte-addressable, techniques such as read-modify-write and caching used to enhance traditional SSDs are not needed to obtain high performance. In addition, chipsets such as Cascade Lake are designed with inbuilt support for 3D XPoint, that allow it to be used as a caching or acceleration disk, and it is also fast enough to be used as non-voltatile RAM (NVRAM) in a DIMM package.

Despite the initial lukewarm reception when first released, 3D XPoint – particularly in the form of Intel's Optane range – has been highly acclaimed and widely recommended for tasks where its specific features are of value, with reviewers such as Storage Review concluding in August 2018 that for low-latency workloads, 3D XPoint was producing 500,000 4K sustained IOPS for both reads and writes, with 3–15 microsecond latencies, and that at present "there is currently nothing [else] that comes close", while Tom's Hardware described the Optane 900p in December 2017 as being like a "mythical creature" that must be seen to be believed, and which doubled the speed of the best previous consumer devices. ServeTheHome concluded in 2017 that in read, write and mixed tests, Optane SSDs were consistently around 2.5× as fast as the best Intel datacentre SSDs which had preceded them, the P3700 NVMe. AnandTech noted that consumer Optane based SSDs were similar in performance to the best non-3D-XPoint SSDs for large transfers, with both being "blown away" by the large transfer performance of enterprise Optane SSDs.

Conductive atomic force microscopy

Conductive atomic force microscopy (C-AFM) or current sensing atomic force microscopy (CS-AFM) is a mode in atomic force microscopy (AFM) that simultaneously measures the topography of a material and the electric current flow at the contact point of the tip with the surface of the sample. The topography is measured by detecting the deflection of the cantilever using an optical system (laser + photodiode), while the current is detected using a current-to-voltage preamplifier. The fact that the CAFM uses two different detection systems (optical for the topography and preamplifier for the current) is a strong advantage compared to scanning tunneling microscopy (STM). Basically, in STM the topography picture is constructed based on the current flowing between the tip and the sample (the distance can be calculated depending on the current). Therefore, when a portion of a sample is scanned with an STM, it is not possible to discern if the current fluctutations are related to a change in the topography (due to surface roughness) or to a change in the sample conductivity (due to intrinsic inhomogeneities).

The CAFM is usually operated in contact mode; the tip can be kept at one location while the voltage and current signals are applied/read, or it can be moved to scan a specific region of the sample under a constant voltage (and the current is collected). Recently, some manufacturers provide the option of measuring the current in semi-contact mode. The CAFM was first developed by John O'Shea and co-workers at the University of Cambridge in 1993, and it is referred to in the literature by several names, including C-AFM, local-conductivity AFM (LC-AFM), conductive probe AFM (CP-AFM), conductive scanning probe microscopy (C-SPM) or conductive scanning force microscopy (C-SFM), although CAFM is the most widespread.

Crossbar (computer hardware manufacturer)

Crossbar is a company based in Santa Clara, California. Crossbar develops a class of non-volatile resistive random-access memory (RRAM) technology.

The company in 2013 announced its goal was a terabyte of storage on a single integrated circuit, compatible with standard CMOS semiconductor manufacturing processes.


Double Data Rate 4 Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR4 SDRAM, is a type of synchronous dynamic random-access memory with a high bandwidth ("double data rate") interface.

Released to the market in 2014, it is one of the latest variants of dynamic random-access memory (DRAM), of which some have been in use since the early 1970s, and a higher-speed successor to the DDR2 and DDR3 technologies.

DDR4 is not compatible with any earlier type of random-access memory (RAM) due to different signaling voltage and physical interface, besides other factors.

DDR4 SDRAM was released to the public market in Q2 2014, focusing on ECC memory, while the non-ECC DDR4 modules became available in Q3 2014, accompanying the launch of Haswell-E processors that require DDR4 memory.


KAIST (formally the Korea Advanced Institute of Science and Technology) is a national research university located in Daedeok Innopolis, Daejeon, South Korea. KAIST was established by the Korean government in 1971 as the nation's first research-oriented science and engineering institution. KAIST also has been internationally accredited in business education, and hosting the Secretariat of AAPBS. KAIST has approximately 10,200 full-time students and 1,140 faculty researchers and had a total budget of US$765 million in 2013, of which US$459 million was from research contracts.

From 1980 to 2008, the institute was known as the Korea Advanced Institute of Science and Technology. In 2008, the name was shortened to "KAIST".

In 2007, KAIST partnered with international institutions and adopted dual degree programs for its students. Its partner institutions include the Technical University of Denmark, Carnegie Mellon University, the Georgia Institute of Technology (Georgia Tech), the Technical University of Berlin, and the Technical University of Munich.

List of Korean inventions and discoveries

This is a list of Korean inventions and discoveries. The Koreans have made contributions across a number of scientific and technological domains. In particular, the country has played a role in the modern Digital Revolution through its large electronics industry with a number of modern revolutionary and widespread technologies in fields such as electronics and robotics introduced by Korean scientists, inventors, and entrepreneurs.

Magnetoresistive random-access memory

Magnetoresistive random-access memory (MRAM) is a type of non-volatile random-access memory which stores data in magnetic domains. Developed in the mid-1980s, proponents have argued that magnetoresistive RAM will eventually surpass competing technologies to become a dominant or even universal memory. Presently, other memory technologies such as flash RAM and DRAM have practical advantages that have so far kept MRAM in a niche role in the market. It is currently in production by Everspin Technologies, and other companies, including GlobalFoundries and Samsung, have announced in 2016 product plans. A recent, comprehensive review article on magnetoresistance and magnetic random access memories is available as an open access paper in Materials Today.


A memristor (; a portmanteau of memory resistor) is a hypothetical non-linear passive two-terminal electrical component relating electric charge and magnetic flux linkage. It was envisioned, and its name coined, in 1971 by circuit theorist Leon Chua.

According to the characterizing mathematical relations, the memristor would hypothetically operate in the following way: the memristor's electrical resistance is not constant but depends on the history of current that had previously flowed through the device, i.e., its present resistance depends on how much electric charge has flowed in what direction through it in the past; the device remembers its history—the so-called non-volatility property. When the electric power supply is turned off, the memristor remembers its most recent resistance until it is turned on again.In 2008, a team at HP Labs claimed to have found Chua's missing memristor based on an analysis of a thin film of titanium dioxide thus connecting the operation of ReRAM devices to the memristor concept. The HP result was published in the scientific journal Nature.

Following this claim, Leon Chua has argued that the memristor definition could be generalized to cover all forms of two-terminal non-volatile memory devices based on resistance switching effects. Chua also argued that the memristor is the oldest known circuit element, with its effects predating the resistor, capacitor, and inductor. There are, however, some serious doubts as to whether a genuine memristor can actually exist in physical reality. Additionally, some experimental evidence contradicts Chua's generalization since a non-passive nanobattery effect is observable in resistance switching memory. A simple test has been proposed by Pershin and Di Ventra to analyse whether such an ideal or generic memristor does actually exist or is a purely mathematical concept. Up to now, there seems to be no experimental resistance switching device (ReRAM) which can pass the test.These devices are intended for applications in nanoelectronic memories, computer logic, and neuromorphic/neuromemristive computer architectures. In 2013, Hewlett-Packard CTO Martin Fink suggested that memristor memory may become commercially available as early as 2018. In March 2012, a team of researchers from HRL Laboratories and the University of Michigan announced the first functioning memristor array built on a CMOS chip.

Nickel oxides

Nickel forms a series of mixed oxide compounds which are commonly called nickelates.

A nickelate is an anion containing nickel or a salt containing a nickelate anion, or a double compound containing nickel bound to oxygen and other elements. Nickel can be in different or even mixed oxidation states, ranging from +1, +2, +3 to +4. The anions can contain a single nickel ion, or multiple to form a cluster ion. The solid mixed oxide compounds are often ceramics, but can also be metallic. They have a variety of electrical and magnetic properties. Rare-earth elements form a range of perovskite nickelates, in which the properties vary systematically as the rare-earth element changes. Fine tuning of properties is achievable with mixtures of elements, applying stress or pressure, or varying the physical form.

Inorganic chemists call many compounds that contain nickel centred anions "nickelates". These include the chloronickelates, fluoronickelates, tetrabromonickelates, tetraiodonickelates, cyanonickelates, nitronickelates and other nickel-organic acid complexes such as oxalatonickelates.

Spin-transfer torque

Spin-transfer torque is an effect in which the orientation of a magnetic layer in a magnetic tunnel junction or spin valve can be modified using a spin-polarized current.

Charge carriers (such as electrons) have a property known as spin which is a small quantity of angular momentum intrinsic to the carrier. An electric current is generally unpolarized (consisting of 50% spin-up and 50% spin-down electrons); a spin polarized current is one with more electrons of either spin. By passing a current through a thick magnetic layer (usually called the “fixed layer”), one can produce a spin-polarized current. If this spin-polarized current is directed into a second, thinner magnetic layer (the “free layer”), the angular momentum can be transferred to this layer, changing its orientation. This can be used to excite oscillations or even flip the orientation of the magnet. The effects are usually seen only in nanometer scale devices.

Universal memory

Universal memory refers to a computer data storage device combining the cost benefits of DRAM, the speed of SRAM, the non-volatility of flash memory along with infinite durability. Such a device, if it ever becomes possible to develop, would have a far-reaching impact on the computer market.

Computers for most of their recent history have depended on several different data storage technologies simultaneously as part of their operation. Each one operates at a level in the memory hierarchy where another would be unsuitable. A personal computer might include a few megabytes of fast but volatile and expensive SRAM as the CPU cache, several gigabytes of slower DRAM for program memory, and multiple hundreds of gigabytes of the slow but non-volatile flash memory or a few terabytes of "spinning platters" hard disk drive for long term storage. For example, a university recommended students entering in 2015–2016 to have a PC with:

- a CPU with a 4×256 KB L2 cache, and a 6 MB L3 cache

- 16 GB DRAM

- 256 GB solid-state drive, and

- 1 TB hard disk driveResearchers seek to replace these different memory types with one single type to reduce the cost and increase performance. For a memory technology to be considered a universal memory, it would need to have best characteristics of several memory technologies. It would need to:

- operate very quickly – like SRAM cache

- support a practically unlimited number of read/write cycles – like SRAM and DRAM

- retain data indefinitely without using power – like flash memory and hard disk drives, and

- be sufficiently large for common operating systems and application programs, yet affordable – like hard disk drives.The last criterion is likely to be satisfied last, as economies of scale in manufacturing reduce cost. Many types of memory technologies have been explored with the goal of creating a practical universal memory. These include:

low-voltage, non-volatile, compound-semiconductor memory (demonstrated)

magnetoresistive random-access memory (MRAM) (in development and production)

bubble memory (1970-1980, obsolete)

racetrack memory (currently experimental)

ferroelectric random-access memory (FRAM) (in development and production)

phase-change memory (PCM)

programmable metallization cell (PMC)

resistive random-access memory (RRAM)


memristor-based memorySince each memory has its limitations, none of these have yet reached the goals of universal memory.



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