Processor register

In computer architecture, a processor register is a quickly accessible location available to a computer's central processing unit (CPU). Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-only. Registers are typically addressed by mechanisms other than main memory, but may in some cases be assigned a memory address e.g. DEC PDP-10, ICT 1900.

Almost all computers, whether load/store architecture or not, load data from a larger memory into registers where it is used for arithmetic operations and is manipulated or tested by machine instructions. Manipulated data is then often stored back to main memory, either by the same instruction or by a subsequent one. Modern processors use either static or dynamic RAM as main memory, with the latter usually accessed via one or more cache levels.

Processor registers are normally at the top of the memory hierarchy, and provide the fastest way to access data. The term normally refers only to the group of registers that are directly encoded as part of an instruction, as defined by the instruction set. However, modern high-performance CPUs often have duplicates of these "architectural registers" in order to improve performance via register renaming, allowing parallel and speculative execution. Modern x86 design acquired these techniques around 1995 with the releases of Pentium Pro, Cyrix 6x86, Nx586, and AMD K5.

A common property of computer programs is locality of reference, which refers to accessing the same values repeatedly and holding frequently used values in registers to improve performance; this makes fast registers and caches meaningful.[1] Allocating frequently used variables to registers can be critical to a program's performance; this register allocation is performed either by a compiler in the code generation phase, or manually by an assembly language programmer.

Register size

Registers are normally measured by the number of bits they can hold, for example, an "8-bit register", "32-bit register" or a "64-bit register" or even more. In some instruction sets, the registers can operate in various modes breaking down its storage memory into smaller ones (32-bit into four 8-bit one for instance) to which multiple data (vector, or one dimensional array of data) can be loaded and operated upon at the same time. Typically it is implemented by adding extra registers that map their memory into bigger one. Processors that have the ability to execute single instruction on multiple data are called vector processors.

Types of registers

A processor often contains several kinds of registers, which can be classified according to their content or instructions that operate on them:

  • User-accessible registers can be read or written by machine instructions. The most common division of user-accessible registers is into data registers and address registers.
    • Data registers can hold numeric data values such as integer and, in some architectures, floating-point values, as well as characters, small bit arrays and other data. In some older and low end CPUs, a special data register, known as the accumulator, is used implicitly for many operations.
    • Address registers hold addresses and are used by instructions that indirectly access primary memory.
      • Some processors contain registers that may only be used to hold an address or only to hold numeric values (in some cases used as an index register whose value is added as an offset from some address); others allow registers to hold either kind of quantity. A wide variety of possible addressing modes, used to specify the effective address of an operand, exist.
      • The stack pointer is used to manage the run-time stack. Rarely, other data stacks are addressed by dedicated address registers, see stack machine.
    • General-purpose registers (GPRs) can store both data and addresses, i.e., they are combined data/address registers and rarely the register file is unified to include floating point as well.
    • Status registers hold truth values often used to determine whether some instruction should or should not be executed.
    • Floating-point registers (FPRs) store floating point numbers in many architectures.
    • Constant registers hold read-only values such as zero, one, or pi.
    • Vector registers hold data for vector processing done by SIMD instructions (Single Instruction, Multiple Data).
    • Special-purpose registers (SPRs) hold program state; they usually include the program counter, also called the instruction pointer, and the status register; the program counter and status register might be combined in a program status word (PSW) register. The aforementioned stack pointer is sometimes also included in this group. Embedded microprocessors can also have registers corresponding to specialized hardware elements.
    • In some architectures, model-specific registers (also called machine-specific registers) store data and settings related to the processor itself. Because their meanings are attached to the design of a specific processor, they cannot be expected to remain standard between processor generations.
    • Memory Type Range Registers (MTRRs)
  • Internal registers – registers not accessible by instructions, used internally for processor operations.
  • Architectural register - The registers visible to software defined by an architecture may not correspond to the physical hardware, if there is register renaming being performed by underlying hardware.

Hardware registers are similar, but occur outside CPUs.

In some architectures (such as SPARC and MIPS), the first or last register in the integer register file is a pseudo-register in a way that it is hardwired to always return zero when read (mostly to simplify indexing modes), and it cannot be overwritten. In Alpha this is also done for the floating-point register file. As a result of this, register files are commonly quoted as having one register more than how many of them are actually usable; for example, 32 registers are quoted when only 31 of them fit within the above definition of a register.

Examples

The following table shows the number of registers in several mainstream CPU architectures. Note that in x86-compatible processors the stack pointer (ESP) is counted as an integer register, even though there are a limited number of instructions that may be used to operate on its contents. Similar caveats apply to most architectures.

Although all of the above listed architectures are different, almost all are a basic arrangement known as the Von Neumann architecture, first proposed by the Hungarian-American mathematician John von Neumann. It is also noteworthy that the number of registers on GPUs is much higher than that on CPUs.[1][2]

Architecture GPRs/data+address registers FP
registers
Notes
AT&T Hobbit 0 stack of 7 Stack machine
Cray-1[3] 8 scalar data, 8 address 8 scalar, 8 vector (64 elements) Scalar data registers can be integer or floating-point; also 64 scalar scratch-pad T registers and 64 address scratch-pad B registers
4004[4] 1 accumulator, 16 others 0 Register A is for general purpose, while r0–r15 registers are for the address and segment.
8008[5] 1 accumulator, 6 others 0 The A register is an accumulator to which all arithmetic is done; the H and L registers can be used in combination as an address register; all registers can be used as operands in load/store/move/increment/decrement instructions and as the other operand in arithmetic instructions. There is no FP unit available.
8080[6] 1 accumulator, 6 others 0 Plus a stack pointer. The A register is an accumulator to which all arithmetic is done; the register pairs B+C, D+E, and H+L, can be used as address registers in some instructions; all registers can be used as operands in load/store/move/increment/decrement instructions and as the other operand in arithmetic instructions. Some instructions only use H+L; another instruction swaps H+L and D+E. Floating point processors intended for the 8080 were Intel 8231, AMD Am9511 and Intel 8232. They were also readily usable with the Z80 and similar processors.
iAPX432 0 stack of 6 Stack machine
16-bit x86[7] 8 stack of 8 (if FP present) 8086/8088, 80186/80188, 80286, with 8087, 80187 or 80287 for floating-point, with an 80-bit wide, 8 deep register stack with some instructions able to use registers relative to the top of the stack as operands; without 8087/80187/80287, no floating-point registers
IA-32[8] 8 stack of 8 (if FP present), 8 (if SSE/MMX present) 80386 required 80387 for floating-point, later processors had built-in floating point, with both having an 80-bit wide, 8 deep register stack with some instructions able to use registers relative to the top of the stack as operands. The Pentium III and later had the SSE with additional 128-bit XMM registers.
x86-64[8][9] 16 16/32 FP registers are 128-bit XMM registers, later extended to 256-bit YMM registers with AVX/AVX2 and 512-bit ZMM0-ZMM31 registers with AVX-512.[10]
Xeon Phi[11] 16 32 Including 32 256/512-bit ZMM registers with AVX-512.
Fairchild F8 one accumulator, 64 scratchpad registers, one indirect scratchpad register (ISAR) n/a Instructions can directly reference the first 16 scratchpad registers and can access all scratchpad registers indirectly through the ISAR[12]
Geode GX 1 data, 1 address 8 Geode GX/Media GX/4x86/5x86 is the emulation of 486/Pentium compatible processor made by Cyrix/National Semiconductor. Like Transmeta, the processor had a translation layer that translated x86 code to native code and executed it. It does not support 128-bit SSE registers, just the 80387 stack of eight 80-bit floating point registers, and partially support 3DNow! from AMD. The native processor only contains 1 data and 1 address register for all purpose and translated into 4 paths of 32-bit naming register r1 (base), r2 (data), r3 (back pointer), and r4 (stack pointer) within scratchpad sram for integer operation and uses the L1 cache for x86 code emulation(note that it's not compatible with some 286/386/486 instructions in real mode). Later the design was abandoned after AMD acquired the IP from National Semiconductor and branded it with Athlon core in embedded market.
SunPlus SPG 0 6 stack + 4 SIMD A 16-bit wide, 32-bit address space stack machine processor that made from Taiwanese semiconductor called "Sunplus", it can be found on Vtech's v'smile line for educational purpose and video game console like Mattel hyperscan, XaviXPORT. it does lack any general purpose register or internal register for naming/renaming but its Floating Point Unit has 80-bit 6 stage stack and four 128-bit VLIW SIMD register on a vertex shader co-processor.
VM Labs Nuon 0 1 a 32-bit stack machine processor that developed by VM labs for specialized on multimedia purpose. It can be found on the company's own Nuon DVD player console line and Game Wave Family Entertainment System from ZaPit games. The design was heavy influence by Intel's MMX technology, it contained a 128 bytes unified stack cache for both vector and scalar instructions. the unified cache can be divided as 8 128-bit vector register or 32 32bit SIMD scalar register through bank renaming, no integer register found in this architecture.
Nios II[13][14] 31 8 Nios II is based on MIPS IV instruction set and has 31 32-bit GPRs, with register 0 being hardwired to zero and 8 64-bit floating point registers
Motorola 6800[15] 2 data, 1 index 0 Plus a stack pointer
Motorola 68k[16] 8 data (d0-d7), 8 address (a0-a7) 8 (if FP present) Address register 8 (a7) is the stack pointer. 68000, 68010, 68012, 68020, and 68030 require an FPU for floating point; 68040 had FPU built in. FP registers are 80-bit.
SH 16-bit 1 6
Emotion Engine 3(VU0)+ 32(VU1) 32 SIMD(integrated in UV1) + 2x 32 Vector (dedicated vector co-processor that located near by its GPU) The Emotion Engine's main core (VU0) is a heavily modified DSP general core that's for general background task and it contains one 64 bit accumulator, two general data registers and one 32 bit program counter. A modified MIPS III executable core(VU1) is for game data and protocol control and it contains 32 entries 32-bit general-purpose registers for integer computation and 32 entries 128-bit SIMD registers for storing SIMD instruction, streaming data value and some integer calculation value. one accumulator register for connecting general floating-point computation to vector register file on co-processor. The coprocessor is built via 32 entries 128-bit vector register file(can only store vector value that pass from accumulator in cpu. ) and no integer register is built in. Both vector co-processor(VPU 0/1) and emotion engine's entire main processor module(VU0 + VU1 + VPU0 + VPU1) are built based on modified MIPS instructions set and accumulator in this case is not general purpose but control status.
CUDA 1 8/16/32/64/128 Each CUDA core contains a single 32/64-bit integer data register while the floating point unit contains a much larger number of registers:
  • the Tesla 1.0-based G8x contains 8×128-bit HDR vector registers,
  • the Tesla 2.0-based GT200 increased the count to 16×128-bit
  • Fermi extended the register width to 256 bits and increased the register count to 32, (32×256-bit)
  • Kepler increased it to 64. (64×256-bit)
  • Maxwell contains a massive amount of 128 512-bit vector registers. (128×512-bit)
  • Pascal: ?
  • Volta: ?
IBM/360 16 4 (if FP present) This applies to S/360's successors, System/370 through System/390; FP was optional in System/360, and always present in S/370 and later. In processors with the Vector Facility, there are 16 vector registers containing a machine-dependent number of 32-bit elements.[17]
z/Architecture 16 16 64-bit version of S/360 and successors; it increased the number of floating-point registers to 16.
MMIX[18] 256 256 An instruction set designed by Donald Knuth in the late 1990s for pedagogical purposes.
NS320xx[19] 8 8 (if FP present)
Xelerated X10 1 32 a 32/40 bit stack machine based network processor with modified MIPS instruction and 128 bit floating point unit.
Parallax Propeller 0 2 An eight core 8/16 bit sliced stack machine controller with simple logic circus inside, have eight cog counter(core) and each contain three 8/16 bit special control registers with 32 bit x 512 stack ram however it does not carrying any general register for integer purpose. unlike most of shadow register file in modern processor and multi core system, all these stack ram in cog can be accessed in instruction level which all these cog can act as one big single general purpose core if necessary. Floating point unit is external and it contain two 80 bit vector register.
Itanium 128 128 And 64 1-bit predicate registers and 8 branch registers. The FP registers are 82-bit.
SPARC 31 32 Global register 0 is hardwired to 0. Uses register windows.
IBM POWER 32 32 And 1 link and 1 count register.
Power ISA 32 32 And 1 link and 1 count register. Processors supporting the Vector facility also have 32 128-bit vector registers,
Blackfin 8 16 containing two external uncore 40 bit accumulator, but non are general purpose. Support 64 bit RISC architecture ISA, vector register are 256 bit.
IBM Cell SPE 128 128 GPRs, which can hold integer, address, or floating-point values[20]
PDP-10 16 0 All may be used generally (integer, float, stack pointer, jump, indexing, etc.). Every 36-bit memory (or register) word can also be manipulated as a half-word, which can be considered an (18-bit) address. Other word interpretations are used by certain instructions. In the original PDP-10 processors, these 16 GPRs also corresponded to main (i.e. core) memory locations 0-15; a hardware option called "fast memory" implemented the registers as separate ICs, and references to memory locations 0-15 referred to the IC registers. Later models implemented the registers as "fast memory" and continued to make memory locations 0-15 refer to them. Movement instructions take (register, memory) operands: MOVE 1,2 is register-register, and MOVE 1,1000 is memory-to-register.
PDP-11 8 0 R7 is actually the Program Counter. Any register can be a stack pointer but R6 is used for hardware interrupts and traps.
VAX 16 0 Three of the registers have special uses: R12 (Argument Pointer), R13 (Frame Pointer), and R14 (Stack Pointer), while R15 refers to the Program Counter.
Alpha 31 31 Registers R31 (integer) and F31 (floating-point) are hardwired to zero.
6502 1 data, 2 index 0 6502's content A (Accumulator) register for main purpose data store and memory address (8-bit data/16-bit address), X,Y are indirect and direct index registers (respectively) and SP register are specific index only.
W65C816S 1 0 65C816 is the 16-bit successor of the 6502. X,Y, D (Direct Page register) are condition register and SP register are specific index only. main accumulator extended to 16-bit (B) while keep 8-bit (A) for compatibility and main register can now address up to 24-bit (16-bit wide data instruction/24-bit memory address).
65k 1 0 Direct successor of 6502, 65002 only content A (Accumulator) register for main purpose data store and extend data wide to 32-bit and 64-bit instruction wide, support 48-bit virtual address in software mode, X,Y are still condition register and remain 8-bit and SP register are specific index but increase to 16-bit wide.
MeP 4 8 Media-embedded processor was a 32 bit processor developed by toshiba, a modded 8080 instruction set with only A, B, C, D register available through all mode(8/16/32 bit) and incompatible with x86, however it contain 80 bit floating point unit that is x87 compatible.
PIC microcontroller 1 0
AVR microcontroller 32 0
ARM 32-bit (ARM/A32, Thumb/T32) 14 Varies (up to 32) r15 is the program counter, and not usable as a GPR; r13 is the stack pointer; r8-r13 can be switched out for others (banked) on a processor mode switch. Older versions had 26-bit addressing,[21] and used upper bits of the program counter (r15) for status flags, making that register 32-bit.
ARM 64-bit (A64)[22] 31 32 Register r31 is the stack pointer or hardwired to 0, depending on the context.
MIPS 31 32 Register 0 is hardwired to 0.
Epiphany 64 (per core)[23] Each instruction controls whether registers are interpreted as integers or single precision floating point. Architecture is scalable to 4096 cores with 16 and 64 core implementations currently available.

Register usage

The number of registers available on a processor and the operations that can be performed using those registers has a significant impact on the efficiency of code generated by optimizing compilers. The Strahler number of an expression tree gives the minimum number of registers required to evaluate that expression tree.

See also

References

  1. ^ a b "A Survey of Techniques for Designing and Managing CPU Register File". Concurrency and Computation. Wiley. 2016. doi:10.1002/cpe.3906.
  2. ^ "A Survey of Techniques for Architecting and Managing GPU Register File", IEEE TPDS, 2016
  3. ^ "Cray-1 Computer System Hardware Reference Manual" (PDF). Cray Research. November 1977.
  4. ^ "MCS-4 Micro Computer Set Users Manual" (PDF). Intel. February 1973.
  5. ^ "8008 8 Bit Parallel Central Processor Unit Users Manual" (PDF). Intel. November 1973. Retrieved January 23, 2014.
  6. ^ "Intel 8080 Microcomputer Systems User's Manual" (PDF). Intel. September 1975. Retrieved January 23, 2014.
  7. ^ "80286 and 80287 Programmer's Reference Manual" (PDF). Intel. 1987.
  8. ^ a b "Intel 64 and IA-32 Architectures Software Developer Manuals". Intel.
  9. ^ "AMD64 Architecture Programmer's Manual Volume 1: Application Programming" (PDF). AMD. October 2013.
  10. ^ "Intel Architecture Instruction Set Extensions and Future Features Programming Reference" (PDF). Intel. January 2018.
  11. ^ "Intel Xeon Phi Coprocessor Instruction Set Architecture Reference Manual" (PDF). Intel. September 7, 2012.
  12. ^ F8 Guide to Programming (PDF). Fairchild MOS Microcomputer Division. 1977.
  13. ^ "Nios II Classic Processor Reference Guide" (PDF). Altera. April 2, 2015.
  14. ^ "Nios II Gen2 Processor Reference Guide" (PDF). Altera. April 2, 2015.
  15. ^ "M6800 Programming Reference Manual" (PDF). Motorola. November 1976. Retrieved May 18, 2015.
  16. ^ "Motorola M68000 Family Programmer's Reference Manual" (PDF). Motorola. 1992. Retrieved June 13, 2015.
  17. ^ "IBM Enterprise Systems Architecture/370 and System/370 - Vector Operations" (PDF). IBM. Retrieved January 5, 2014.
  18. ^ "MMIX Home Page".
  19. ^ "Series 32000 Databook" (PDF). National Semiconductor.
  20. ^ "Synergistic Processor Unit Instruction Set Architecture Version 1.2" (PDF). IBM. January 27, 2007.
  21. ^ "Procedure Call Standard for the ARM Architecture" (PDF). ARM Holdings. 30 November 2013. Retrieved 27 May 2013.
  22. ^ "Procedure Call Standard for the ARM 64-bit Architecture" (PDF). ARM Holdings. 22 May 2013. Retrieved 27 May 2013.
  23. ^ "Epiphany Architecture Reference" (PDF).
Accumulator

Accumulator may refer to:

Accumulator (bet), a parlay bet

Accumulator (computing), in a CPU, a processor register for storing intermediate results

Accumulator (computer vision), discrete cell structure to count votes, standard component of the Hough transform

Accumulator (cryptography), a value, determined by a set of values, that allows you to verify if any one of the original values is a member of the set

Accumulator (energy), an apparatus for storing energy or power

Capacitor, in electrical engineering, also known by the obsolete term accumulator

Electrochemical cell, a cell that stores electrical energy, typically used in rechargeable batteries

Hydraulic accumulator, an energy storage device using hydraulic fluid under pressure

Accumulator (structured product), a financial contract used by clients (usually individuals) to accumulate stock positions over time

Accumulator 1, a Czech film

Dynamic accumulator, a plant that mines nutrients from the soil through its roots

Arbitrary-precision arithmetic

In computer science, arbitrary-precision arithmetic, also called bignum arithmetic, multiple-precision arithmetic, or sometimes infinite-precision arithmetic, indicates that calculations are performed on numbers whose digits of precision are limited only by the available memory of the host system. This contrasts with the faster fixed-precision arithmetic found in most arithmetic logic unit (ALU) hardware, which typically offers between 8 and 64 bits of precision.

Several modern programming languages have built-in support for bignums, and others have libraries available for arbitrary-precision integer and floating-point math. Rather than store values as a fixed number of binary bits related to the size of the processor register, these implementations typically use variable-length arrays of digits.

Arbitrary precision is used in applications where the speed of arithmetic is not a limiting factor, or where precise results with very large numbers are required. It should not be confused with the symbolic computation provided by many computer algebra systems, which represent numbers by expressions such as π·sin(2), and can thus represent any computable number with infinite precision.

Arithmetic logic unit

An arithmetic logic unit (ALU) is a combinational digital electronic circuit that performs arithmetic and bitwise operations on integer binary numbers. This is in contrast to a floating-point unit (FPU), which operates on floating point numbers. An ALU is a fundamental building block of many types of computing circuits, including the central processing unit (CPU) of computers, FPUs, and graphics processing units (GPUs). A single CPU, FPU or GPU may contain multiple ALUs.

The inputs to an ALU are the data to be operated on, called operands, and a code indicating the operation to be performed; the ALU's output is the result of the performed operation. In many designs, the ALU also has status inputs or outputs, or both, which convey information about a previous operation or the current operation, respectively, between the ALU and external status registers.

Bit specification

In computing, bit specification may mean:

Computer hardware or software capabilities or design features expressed in terms of bit counts. Higher bit specification (e.g. 16-bit vs. 8-bit) usually indicates better performance. Examples:

Color depth

Computer bus size

Processor register size

Sound quality

Specification or datasheet where the meaning of individual bits in a larger, for example byte-length, message is described. Bit specifications are often required to document low-level device control or data transmission protocols. See bit manipulation.

Computer number format

A computer number format is the internal representation of numeric values in digital computer and calculator hardware and software. Normally, numeric values are stored as groupings of bits, named for the number of bits that compose them. The encoding between numerical values and bit patterns is chosen for convenience of the operation of the computer; the bit format used by the computer's instruction set generally requires conversion for external use such as printing and display. Different types of processors may have different internal representations of numerical values. Different conventions are used for integer and real numbers. Most calculations are carried out with number formats that fit into a processor register, but some software systems allow representation of arbitrarily large numbers using multiple words of memory.

Control register

A control register is a processor register which changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, and coprocessor control.

DOS API

The DOS API is an API which originated with 86-DOS and is used in MS-DOS/PC DOS and other DOS-compatible operating systems. Most calls to the DOS API are invoked using software interrupt 21h (INT 21h). By calling INT 21h with a subfunction number in the AH processor register and other parameters in other registers, one invokes various DOS services. DOS services include handling keyboard input, video output, disk file access, program execution, memory allocation, and various other activities. In the late 1980s, DOS extenders along with the DOS Protected Mode Interface (DPMI) allow the programs to run in either 16-bit or 32-bit protected mode and still have access to the DOS API.

Data (computing)

Data ( DAY-tə, DAT-ə, DAH-tə; treated as singular, plural, or as a mass noun) is any sequence of one or more symbols given meaning by specific act(s) of interpretation.

Data (or datum – a single unit of data) requires interpretation to become information. To translate data to information, there must be several known factors considered. The factors involved are determined by the creator of the data and the desired information. The term metadata is used to reference the data about the data. Metadata may be implied, specified or given. Data relating to physical events or processes will also have a temporal component. In almost all cases this temporal component is implied. This is the case when a device such as a temperature logger receives data from a temperature sensor. When the temperature is received it is assumed that the data has a temporal references of "now". So the device records the date, time and temperature together. When the data logger communicates temperatures, it must also report the date and time (metadata) for each temperature.

Digital data is data that is represented using the binary number system of ones (1) and zeros (0), as opposed to analog representation. In modern (post 1960) computer systems, all data is digital. Data within a computer, in most cases, moves as parallel data. Data moving to or from a computer, in most cases, moves as serial data. See Parallel communication and Serial communication. Data sourced from an analog device, such as a temperature sensor, must pass through an "analog to digital converter" or "ADC" (see Analog-to-digital converter) to convert the analog data to digital data.

Data representing quantities, characters, or symbols on which operations are performed by a computer are stored and recorded on magnetic, optical, or mechanical recording media, and transmitted in the form of digital electrical signals.A program is a set of data that consists of a series of coded software instructions to control the operation of a computer or other machine. Physical computer memory elements consist of an address and a byte/word of data storage. Digital data are often stored in relational databases, like tables or SQL databases, and can generally be represented as abstract key/value pairs.

Data can be organized in many different types of data structures, including arrays, graphs, and objects. Data structures can store data of many different types, including numbers, strings and even other data structures. Data pass in and out of computers via peripheral devices.

In an alternate usage, binary files (which are not human-readable) are sometimes called "data" as distinguished from human-readable "text". The total amount of digital data in 2007 was estimated to be 281 billion gigabytes (= 281 exabytes).Digital data comes in these three states: data at rest, data in transit and data in use.

Index register

An index register in a computer's CPU is a processor register used for modifying operand addresses during the run of a program, typically for doing vector/array operations.

The contents of an index register is added to (in some cases subtracted from) an immediate address (one that is part of the instruction itself) to form the "effective" address of the actual data (operand). Special instructions are typically provided to test the index register and, if the test fails, increments the index register by an immediate constant and branches, typically to the start of the loop. Some instruction sets allow more than one index register to be used; in that case additional instruction fields specify which index registers to use. While normally processors that allow an instruction to specify multiple index registers add the contents together, IBM had a line of computers in which the contents were or'd together.In early computers without any form of indirect addressing, array operations had to be performed by modifying the instruction address, which required several additional program steps and used up more computer memory, a scarce resource in computer installations of the early era (as well as in early microcomputers two decades later).

Integer (computer science)

In computer science, an integer is a datum of integral data type, a data type that represents some range of mathematical integers. Integral data types may be of different sizes and may or may not be allowed to contain negative values. Integers are commonly represented in a computer as a group of binary digits (bits). The size of the grouping varies so the set of integer sizes available varies between different types of computers. Computer hardware, including virtual machines, nearly always provide a way to represent a processor register or memory address as an integer.

Machine code

Machine code is a computer program written in machine language instructions that can be executed directly by a computer's central processing unit (CPU). Each instruction causes the CPU to perform a very specific task, such as a load, a store, a jump, or an ALU operation on one or more units of data in CPU registers or memory.

Machine code is a strictly numerical language which is intended to run as fast as possible, and may be regarded as the lowest-level representation of a compiled or assembled computer program or as a primitive and hardware-dependent programming language. While it is possible to write programs directly in machine code, it is tedious and error prone to manage individual bits and calculate numerical addresses and constants manually. For this reason, programs are very rarely written directly in machine code in modern contexts, but may be done for low level debugging, program patching, and assembly language disassembly.

The overwhelming majority of practical programs today are written in higher-level languages or assembly language. The source code is then translated to executable machine code by utilities such as compilers, assemblers, and linkers, with the important exception of interpreted programs, which are not translated into machine code. However, the interpreter itself, which may be seen as an executor or processor, performing the instructions of the source code, typically consists of directly executable machine code (generated from assembly or high-level language source code).

Machine code is by definition the lowest level of programming detail visible to the programmer, but internally many processors use microcode or optimise and transform machine code instructions into sequences of micro-ops. This is not generally considered to be a machine code per se.

Program counter

The program counter (PC), commonly called the instruction pointer (IP) in Intel x86 and Itanium microprocessors, and sometimes called the instruction address register (IAR), the instruction counter, or just part of the instruction sequencer,

is a processor register that indicates where a computer is in its program sequence.In most processors, the PC is incremented after fetching an instruction, and holds the memory address of ("points to") the next instruction that would be executed. (In a processor where the incrementation precedes the fetch, the PC points to the current instruction being executed.)

Processors usually fetch instructions sequentially from memory, but control transfer instructions change the sequence by placing a new value in the PC. These include branches (sometimes called jumps), subroutine calls, and returns. A transfer that is conditional on the truth of some assertion lets the computer follow a different sequence under different conditions.

A branch provides that the next instruction is fetched from elsewhere in memory. A subroutine call not only branches but saves the preceding contents of the PC somewhere. A return retrieves the saved contents of the PC and places it back in the PC, resuming sequential execution with the instruction following the subroutine call.

Quantum register

In quantum computing, a quantum register

is a system comprising multiple qubits. It is the quantum analog of the classical processor register. Quantum computers perform calculations by manipulating qubits within a quantum register.

SWAR

SIMD within a register (SWAR) is a technique for performing parallel operations on data contained in a processor register. SIMD stands for single instruction, multiple data.

Many modern general-purpose computer processors have some provisions for SIMD, in the form of a group of registers and instructions to make use of them. SWAR refers to the use of those registers and instructions, as opposed to using specialized processing engines designed to be better at SIMD operations. It also refers to the use of SIMD with general-purpose registers and instructions that were not meant to do it at the time, by way of various novel software tricks.

Stack register

A stack register is a computer central processor register whose purpose is to keep track of a call stack. On an accumulator-based architecture machine, this may be a dedicated register such as SP on an Intel x86 machine. On a general register machine, it may be a register which is reserved by convention, such as on the PDP-11 or RISC machines. Some designs such as the Data General Eclipse had no dedicated register, but used a reserved hardware memory address for this function.

Machines before the late 1960s—such as the PDP-8 and HP 2100—did not have compilers which supported recursion. Their subroutine instructions typically would save the current location in the jump address, and then set the program counter to the next address. While this is simpler than maintaining a stack, since there is only one return location per subroutine code section, there cannot be recursion without considerable effort on the part of the programmer.

A stack machine has 2 or more stack registers — one of them keeps track of a call stack, the other(s) keep track of other stack(s).

Task state segment

The task state segment (TSS) is a special structure on x86-based computers which holds information about a task. It is used by the operating system kernel for task management. Specifically, the following information is stored in the TSS:

Processor register state

I/O port permissions

Inner-level stack pointers

Previous TSS linkAll this information should be stored at specific locations within the TSS as specified in the IA-32 manuals.

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