In computer architecture, a processor register is a quickly accessible location available to a computer's central processing unit (CPU). Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-only. Registers are typically addressed by mechanisms other than main memory, but may in some cases be assigned a memory address e.g. DEC PDP-10, ICT 1900.
Almost all computers, whether load/store architecture or not, load data from a larger memory into registers where it is used for arithmetic operations and is manipulated or tested by machine instructions. Manipulated data is then often stored back to main memory, either by the same instruction or by a subsequent one. Modern processors use either static or dynamic RAM as main memory, with the latter usually accessed via one or more cache levels.
Processor registers are normally at the top of the memory hierarchy, and provide the fastest way to access data. The term normally refers only to the group of registers that are directly encoded as part of an instruction, as defined by the instruction set. However, modern high-performance CPUs often have duplicates of these "architectural registers" in order to improve performance via register renaming, allowing parallel and speculative execution. Modern x86 design acquired these techniques around 1995 with the releases of Pentium Pro, Cyrix 6x86, Nx586, and AMD K5.
A common property of computer programs is locality of reference, which refers to accessing the same values repeatedly and holding frequently used values in registers to improve performance; this makes fast registers and caches meaningful. Allocating frequently used variables to registers can be critical to a program's performance; this register allocation is performed either by a compiler in the code generation phase, or manually by an assembly language programmer.
Registers are normally measured by the number of bits they can hold, for example, an "8-bit register", "32-bit register" or a "64-bit register" or even more. In some instruction sets, the registers can operate in various modes breaking down its storage memory into smaller ones (32-bit into four 8-bit one for instance) to which multiple data (vector, or one dimensional array of data) can be loaded and operated upon at the same time. Typically it is implemented by adding extra registers that map their memory into bigger one. Processors that have the ability to execute single instruction on multiple data are called vector processors.
A processor often contains several kinds of registers, which can be classified according to their content or instructions that operate on them:
Hardware registers are similar, but occur outside CPUs.
In some architectures (such as SPARC and MIPS), the first or last register in the integer register file is a pseudo-register in a way that it is hardwired to always return zero when read (mostly to simplify indexing modes), and it cannot be overwritten. In Alpha this is also done for the floating-point register file. As a result of this, register files are commonly quoted as having one register more than how many of them are actually usable; for example, 32 registers are quoted when only 31 of them fit within the above definition of a register.
The following table shows the number of registers in several mainstream CPU architectures. Note that in x86-compatible processors the stack pointer (ESP) is counted as an integer register, even though there are a limited number of instructions that may be used to operate on its contents. Similar caveats apply to most architectures.
Although all of the above listed architectures are different, almost all are a basic arrangement known as the Von Neumann architecture, first proposed by the Hungarian-American mathematician John von Neumann. It is also noteworthy that the number of registers on GPUs is much higher than that on CPUs.
|AT&T Hobbit||0||stack of 7||The AT&T Hobbit ATT92010 (around 1992) was a commercial version of the 32-bit CRISP (stack machine) processor with RISC style instruction, inspired by the Bell Labs C Machine project, aimed at a design optimized for the C language, Hobbit has no global registers. Addresses can be memory direct or indirect (for pointers) relative to the stack pointer without extra instructions or operand bits. The cache is not optimized for multiprocessors and FPU is consist with custom ASIC design in IEEE standard.|
|Cray-1||8 scalar data, 8 address||8 scalar, 8 vector (64 elements)||Scalar data registers can be integer or floating-point; also 64 scalar scratch-pad T registers and 64 address scratch-pad B registers|
|4004||1 accumulator, 16 others||0||Register A is for general purpose, while r0–r15 registers are for the address and segment.|
|8008||1 accumulator, 6 others||0||The A register is an accumulator to which all arithmetic is done; the H and L registers can be used in combination as an address register; all registers can be used as operands in load/store/move/increment/decrement instructions and as the other operand in arithmetic instructions. There is no FP unit available.|
|8080||1 accumulator, 6 others||0||Plus a stack pointer. The A register is an accumulator to which all arithmetic is done; the register pairs B+C, D+E, and H+L, can be used as address registers in some instructions; all registers can be used as operands in load/store/move/increment/decrement instructions and as the other operand in arithmetic instructions. Some instructions only use H+L; another instruction swaps H+L and D+E. Floating point processors intended for the 8080 were Intel 8231, AMD Am9511 and Intel 8232. They were also readily usable with the Z80 and similar processors.|
|iAPX432||0||stack of 6||The iAPX 432 was referred to as a micromainframe, designed to be programmed entirely in high-level languages. The instruction set architecture was also entirely new and a significant departure from Intel's previous 8008 and 8080 processors as the iAPX 432 programming model was a stack machine with no visible general-purpose registers. It supported object-oriented programming, garbage collection and multitasking as well as more conventional memory management directly in hardware and microcode. Direct support for various data structures was also intended to allow modern operating systems to be implemented using far less program code than for ordinary processors|
|16-bit x86||8||stack of 8 (if FP present)||8086/8088, 80186/80188, 80286, with 8087, 80187 or 80287 for floating-point, with an 80-bit wide, 8 deep register stack with some instructions able to use registers relative to the top of the stack as operands; without 8087/80187/80287, no floating-point registers|
|IA-32||8||stack of 8 (if FP present), 8 (if SSE/MMX present)||80386 required 80387 for floating-point, later processors had built-in floating point, with both having an 80-bit wide, 8 deep register stack with some instructions able to use registers relative to the top of the stack as operands. The Pentium III and later had the SSE with additional 128-bit XMM registers.|
|x86-64||16||32||FP registers are 128-bit XMM registers, later extended to 256-bit YMM registers with AVX/AVX2 and 512-bit ZMM0-ZMM31 registers with AVX-512.|
|Xeon Phi||16||32||Including 32 256/512-bit ZMM registers with AVX-512.|
|Geode GX||1 data, 1 address||8||Geode GX/Media GX/4x86/5x86 is the emulation of 486/Pentium compatible processor made by Cyrix/National Semiconductor. Like Transmeta, the processor had a translation layer that translated x86 code to native code and executed it. It does not support 128-bit SSE registers, just the 80387 stack of eight 80-bit floating point registers, and partially support 3DNow! from AMD. The native processor only contains 1 data and 1 address register for all purpose and translated into 4 paths of 32-bit naming register r1 (base), r2 (data), r3 (back pointer), and r4 (stack pointer) within scratchpad sram for integer operation and uses the L1 cache for x86 code emulation(note that it's not compatible with some 286/386/486 instructions in real mode). Later the design was abandoned after AMD acquired the IP from National Semiconductor and branded it with Athlon core in embedded market.|
|SunPlus SPG||0||6||A 16-bit wide, 32-bit address space stack machine processor that made from Taiwanese semiconductor called "Sunplus", it can be found on Vtech's v'smile line for educational purpose and video game console like Mattel hyperscan, XaviXPORT. it does lack any general purpose register or internal register for naming/renaming but its Floating Point Unit has 80-bit 6 stage stack.|
|VM Labs Nuon||0||1||a 32-bit stack machine processor that developed by VM labs for specialized on multimedia purpose. It can be found on the company's own Nuon DVD player console line and Game Wave Family Entertainment System from ZaPit games. The design was heavy influence by Intel's MMX technology, it contained a 128 bytes unified stack cache for both vector and scalar instructions. the unified cache can be divided as 8 128-bit vector register or 32 32bit SIMD scalar register through bank renaming, no integer register found in this architecture.|
|Nios II||31||8||Nios II is based on MIPS IV instruction set and has 31 32-bit GPRs, with register 0 being hardwired to zero and 8 64-bit floating point registers|
|Motorola 6800||2 data, 1 index||0||Plus a stack pointer|
|Motorola 68k||8 data (d0-d7), 8 address (a0-a7)||8 (if FP present)||Address register 8 (a7) is the stack pointer. 68000, 68010, 68012, 68020, and 68030 require an FPU for floating point; 68040 had FPU built in. FP registers are 80-bit.|
|Emotion Engine||32||32 SIMD + 32 Vector||The Emotion Engine's main core contains 32 entries 32-bit general-purpose registers for integer computation and 32 entries 128-bit SIMD registers for storing SIMD instruction, streaming data value and some integer calculation value. one accumulator register for connecting general floating-point computation to vector register file on co-processor. The coprocessor is built via 32 entries 128-bit vector register file(can only store vector value that pass from accumulator in cpu. ) and no integer register is built in. Both vector co-processor(VPU 0/1) and emotion engine main processor are built based on modified MIPS instructions set. Accumulator in this case is not general purpose but control status.|
|CUDA||1||8/16/32/64/128||Each CUDA core contains a single 32/64-bit integer data register while the floating point unit contains a much larger number of registers:
|IBM/360||16||4 (if FP present)||This applies to S/360's successors, System/370 through System/390; FP was optional in System/360, and always present in S/370 and later. In processors with the Vector Facility, there are 16 vector registers containing a machine-dependent number of 32-bit elements.|
|z/Architecture||16||16||64-bit version of S/360 and successors|
|MMIX||256||256||An instruction set designed by Donald Knuth in the late 1990s for pedagogical purposes.|
|NS320xx||8||8 (if FP present)|
|Xelerated X10||1||32||a 32/40 bit stack machine based network processor with modified MIPS instruction and 128 bit floating point unit.|
|Parallax Propeller||0||2||An eight core 8/16 bit sliced stack machine controller with simple logic circus inside, have eight cog counter(core) and each contain three 8/16 bit special control registers with 32 bit x 512 stack ram however it does not carrying any general register for integer purpose. unlike most of shadow register file in modern processor and multi core system, all these stack ram in cog can be accessed in instruction level which all these cog can act as one big single general purpose core if necessary. Floating point unit is external and it contain two 80 bit vector register.|
|Itanium||128||128||And 64 1-bit predicate registers and 8 branch registers. The FP registers are 82-bit.|
|SPARC||31||32||Global register 0 is hardwired to 0. Uses register windows.|
|IBM POWER||32||32||And 1 link and 1 count register.|
|Power Architecture||32||32||And 1 link and 1 count register. Processors supporting the Vector facility also have 32 128-bit vector registers,|
|Blackfin||8||16||containing two external uncore 40 bit accumulator, but non are general purpose. Support 64 bit RISC architecture ISA, vector register are 256 bit.|
|IBM Cell SPE||128||128 GPRs, which can hold integer, address, or floating-point values|
|PDP-10||16||0||All may be used generally (integer, float, stack pointer, jump, indexing, etc.). Every 36-bit memory (or register) word can also be manipulated as a half-word, which can be considered an (18-bit) address. Other word interpretations are used by certain instructions. In the original PDP-10 processors, these 16 GPRs also corresponded to main (i.e. core) memory locations 0-15; a hardware option called "fast memory" implemented the registers as separate ICs, and references to memory locations 0-15 referred to the IC registers. Later models implemented the registers as "fast memory" and continued to make memory locations 0-15 refer to them. Movement instructions take (register, memory) operands: |
|PDP-11||8||0||R7 is actually the Program Counter. Any register can be a stack pointer but R6 is used for hardware interrupts and traps.|
|VAX||16||0||Three of the registers have special uses: R12 (Argument Pointer), R13 (Frame Pointer), and R14 (Stack Pointer), while R15 refers to the Program Counter.|
|Alpha||31||31||Registers R31 (integer) and F31 (floating-point) are hardwired to zero.|
|6502||1 data, 2 index||0||6502's content A (Accumulator) register for main purpose data store and memory address (8-bit data/16-bit address), X,Y are indirect and direct index registers (respectively) and SP register are specific index only.|
|W65C816S||1||0||65C816 is the 16-bit successor of the 6502. X,Y, D (Direct Page register) are condition register and SP register are specific index only. main accumulator extended to 16-bit (B) while keep 8-bit (A) for compatibility and main register can now address up to 24-bit (16-bit wide data instruction/24-bit memory address).|
|65k||1||0||Direct successor of 6502, 65002 only content A (Accumulator) register for main purpose data store and extend data wide to 32-bit and 64-bit instruction wide, support 48-bit virtual address in software mode, X,Y are still condition register and remain 8-bit and SP register are specific index but increase to 16-bit wide.|
|MeP||4||8||Media-embedded processor was a 32 bit processor developed by toshiba, a modded 8080 instruction set with only A, B, C, D register available through all mode(8/16/32 bit) and incompatible with x86, however it contain 80 bit floating point unit that is x87 compatible.|
|ARM 32-bit (ARM/A32, Thumb/T32)||14||Varies (up to 32)||r15 is the program counter, and not usable as a GPR; r13 is the stack pointer; r8-r13 can be switched out for others (banked) on a processor mode switch. Older versions had 26-bit addressing, and used upper bits of the program counter (r15) for status flags, making that register 32-bit.|
|ARM 64-bit (A64)||31||32||Register r31 is the stack pointer or hardwired to 0, depending on the context.|
|MIPS||31||32||Register 0 is hardwired to 0.|
|Epiphany||64 (per core)||Each instruction controls whether registers are interpreted as integers or single precision floating point. Architecture is scalable to 4096 cores with 16 and 64 core implementations currently available.|
The number of registers available on a processor and the operations that can be performed using those registers has a significant impact on the efficiency of code generated by optimizing compilers. The Strahler number of an expression tree gives the minimum number of registers required to evaluate that expression tree.