OpenCores is a community developing digital open-source hardware through electronic design automation, with a similar ethos as the free software movement. OpenCores hopes to eliminate redundant design work and slash development costs. A number of companies have been reported as adopting OpenCores IP in chips,[1][2] or as adjuncts to EDA tools.[3][4] OpenCores is also cited from time to time in the electronics press as an example of open source in the electronics hardware community.[5]

OpenCores has always been a commercially owned organization. In 2015, the core active users of OpenCores established the independent Free and Open Source Silicon Foundation (FOSSi), and registered the[6] website as the basis for all future development, independent of commercial control.

OpenCores logo


Damjan Lampret, one of the founders of OpenCores, stated on his website that it began in 1999.[7] The first public record of the new website and its objectives was in EE Times in 2000. [8] Then CNET News reported in 2001.[9] Through the following years it was supported by advertising and sponsorship, including by Flextronics.[1]

In mid-2007 an appeal was put out for a new backer,[10] and that November, Swedish design house ORSoC AB[11] agreed to take over maintenance of the OpenCores website.[12]

EE Times reported in late 2008 that OpenCores had passed the 20,000 subscriber mark.[13] In October 2010 it reached 95,000 registered users and had approximately 800 projects. In July 2012 it reached 150,000 registered users.

During 2015, ORSoC AB formed a joint venture with KNCMiner AB to develop bitcoin mining machines. As this became the primary focus of the business, they were able to spend less time with the project. In response to the growing lack of commitment, the core OpenRISC development team set up the Free and Open Source Silicon Foundation (FOSSi), and registered the website as the basis for all future development, independent of commercial control.[14]


In the absence of a widely accepted open source hardware license, the components produced by the OpenCores initiative use several different software licenses. The most common is the GNU LGPL, which states that any modifications to a component must be shared with the community, while one can still use it together with proprietary components. The less restrictive 3-clause BSD license is also used in some hardware projects, while the GNU GPL is often used for software components, such as models and firmware.

The OpenCores library

The library will consist of design elements from central processing units, memory controllers, peripherals, motherboards, and other components. Emerging semiconductor manufacturers could use the information and license designs for free.

The emphasis is on digital modules called "cores", commonly known as IP Cores. The components are used for creating both custom integrated circuits (ASICs) and FPGAs.

The cores are implemented in the hardware description languages Verilog, VHDL or SystemC which may be synthesized to either silicon or gate arrays.

The project aims at using a common non-proprietary system bus named Wishbone, and most components are nowadays adapted to this bus.

Among the components created by OpenCores contributors are:


In April 2011 OpenCores opened donations[17] for a new project to develop a complete system on a chip design based on the OpenRISC processor and implement it into an ASIC-component. OpenCores affiliated with OpenCores, for example OpenSPARC and LEON.

See also


  1. ^ a b Andrew Orlowski, "Flextronics demos open source chips", The Register, 12 December 2003, [1]
  2. ^ Rick Merritt, "Vivace plans to release HD media processors", EE Times India (online edition), 20 April 2006 [2]
  3. ^ Dylan McGrath, "Firm packages OpenCores IP with EDA tool", EE Times (online edition), 9 January 2006 [3]
  4. ^ "OVP Simulator Smashes SystemC TLM-2.0 Performance Barrier", EDA Cafe, 5 February 2009 [4]
  5. ^ Richard Goering, "Doors 'open' to hardware", EE Times (online edition), 6 June 2005 [5]
  6. ^
  7. ^
  8. ^ Peter Clarke, "Free 32-bit processor core hits the Net", EE Times, 28 February, 2000 [6]
  9. ^ John G Spooner, "Open-source credo moves to chip design", CNET News, 27 March 2001 [7]
  10. ^ Peter Clarke, "OpenCores website, brand up for sale", EE Times Europe (online edition), 25 June 2007 [8]
  11. ^ ORSoC AB
  12. ^ Peter Clarke, "Swedish design house agrees to maintain OpenCores", EE Times Europe (online edition), 28 November 2007 [9]
  13. ^ Anne-Francoise Pele, "OpenCores records 20,000 users", EE Times Europe (online edition), 28 October 2008 [10]
  14. ^ Announcement of FOSSi at ORConf2015, CERN, Genva. schedule and video
  15. ^ risc16f84,risc16f84
  16. ^ zet86,zet86
  17. ^ Call for OpenRISC ASIC donations, 30 April 2011 Archived 1 May 2011 at the Wayback Machine

External links

  • Official website
  • Greenbaum, Eli (2011). "Open Source Semiconductor Core Licensing" (pdf). Harvard Journal of Law & Technology (JOLT). Harvard. 25 (1): 131–157.
AVR microcontrollers

AVR is a family of microcontrollers developed since 1996 by Atmel, acquired by Microchip Technology in 2016. These are modified Harvard architecture 8-bit RISC single-chip microcontrollers. AVR was one of the first microcontroller families to use on-chip flash memory for program storage, as opposed to one-time programmable ROM, EPROM, or EEPROM used by other microcontrollers at the time.

AVR microcontrollers find many applications as embedded systems. They are especially common in hobbyist and educational embedded applications, popularized by their inclusion in many of the Arduino line of open hardware development boards.

Amber (processor core)

The Amber processor core is an ARM architecture-compatible 32-bit reduced instruction set computing (RISC) processor. It is open source, hosted on the OpenCores website, and is part of a movement to develop a library of open source hardware projects.


Debian-Installer is an installation program designed for the Debian Linux distribution. It originally appeared in Debian release 3.1 (Sarge), released on June 6, 2005, although the first release of a Linux distribution it was used with was Skolelinux Venus (1.0).

It is also one of two official installers available for Ubuntu; the other being called Ubiquity (itself based on parts of debian-installer) which was introduced in Ubuntu 6.06 (Dapper Drake).

It makes use of cdebconf (a reimplementation of debconf in C) to perform configuration at install time.

Originally, it was only supported under text-mode and ncurses. A graphical front-end (using GTK+-DirectFB) was first introduced in Debian 4.0 (Etch). Since Debian 6.0 (Squeeze), it is used over Xorg instead of DirectFB.

Free and Open Source Silicon Foundation

The Free and Open Source Silicon Foundation (FOSSi Foundation) is a non-profit foundation with the mission to promote and assist free and open digital hardware designs and their related ecosystems. It was set up by the core OpenRISC development team in response to decreasing support from the commercial owners of the website.

FOSSi operates as an open, inclusive, vendor-independent group. It identifies its mission as the following activities:

support and promote open standards development and their use;

support community events and organize regular events;

encourage industry participation in open source IP design;

assist hobbyists and academic institutions with opening their work to the public; and

support the development and maintenance of a web site, aimed at providing a platform for free and open source silicon.FOSSi is the legal entity, owner of the website, the primary portal for the user community. It holds an annual conference (ORConf) and organizes an annual student design contest.

List of microprocessors

This is a list of microprocessors.

List of semiconductor IP core vendors

The following is a list of major vendors in the business of licensing IP cores.

The top semiconductor IP vendors in the World are Arm, Synopsys, Imagination Technologies and Cadence Design Systems.


The MicroBlaze is a soft microprocessor core designed for Xilinx field-programmable gate arrays (FPGA). As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose memory and logic fabric of Xilinx FPGAs.

Open-source computing hardware

Open-source computing hardware comprises computers and computer components with an open design. They are designed as open-source hardware using open-source principles.

Open-source hardware

Open-source hardware (OSH) consists of physical artifacts of technology designed and offered by the open-design movement . Both free and open-source software (FOSS) and open-source hardware are created by this open-source culture movement and apply a like concept to a variety of components. It is sometimes, thus, referred to as FOSH (free and open-source hardware). The term usually means that information about the hardware is easily discerned so that others can make it – coupling it closely to the maker movement. Hardware design (i.e. mechanical drawings, schematics, bills of material, PCB layout data, HDL source code and integrated circuit layout data), in addition to the software that drives the hardware, are all released under free/libre terms. The original sharer gains feedback and potentially improvements on the design from the FOSH community. There is now significant evidence that such sharing can drive a high return on investment for the scientific community.Since the rise of reconfigurable programmable logic devices, sharing of logic designs has been a form of open-source hardware. Instead of the schematics, hardware description language (HDL) code is shared. HDL descriptions are commonly used to set up system-on-a-chip systems either in field-programmable gate arrays (FPGA) or directly in application-specific integrated circuit (ASIC) designs. HDL modules, when distributed, are called semiconductor intellectual property cores, also known as IP cores.


OpenRISC is a project to develop a series of open source instruction set architectures based on established reduced instruction set computing (RISC) principles. It is the original flagship project of the OpenCores community.

The first (and currently only) architectural description is for the OpenRISC 1000, describing a family of 32 and 64-bit processors with optional floating point and vector processing support, and the OpenRISC 1200 implementation of this was designed by Damjan Lampret in 2000, written in the Verilog hardware description language.The hardware design was released under the GNU Lesser General Public License (LGPL), while the models and firmware were released under the GNU General Public License (GPL).

A reference SoC implementation based on the OpenRISC 1200 was developed, known as ORPSoC (the OpenRISC Reference Platform System-on-Chip). A number of groups have demonstrated ORPSoC and other OR1200 based designs running on FPGAs, and there have been a number of commercial derivatives produced.

OpenRISC 1200

The OpenRISC 1200 (OR1200) is an implementation of the open source OpenRISC 1000 RISC architecture [1].

A synthesizable CPU core, it was for many years maintained by developers at, although, since 2015, that activity has now been taken over by the Free and Open Source Silicon Foundation at the website. The Verilog RTL description is released under the GNU Lesser General Public License (LGPL).


The Open JTAG project is an open source project released under GNU License.

It is a complete hardware and software JTAG reference design, based on a simple hardware composed by a FTDI FT245 USB front-end and an Altera EPM570 MAX II CPLD. The capabilities of this hardware configuration make the Open JTAG device able to output TCK signals at 24 MHz using macro-instructions sent from the host end.

The scope is to give the community a JTAG device not based on the PC parallel port: Open JTAG uses the USB channel to communicate with the internal CPLD, sending macro-instructions as fast as possible. The complete project (Beta version) is available at and the Open JTAG project official site.

Open admissions

Open admissions, or open enrollment, is a type of unselective and noncompetitive college admissions process in the United States in which the only criterion for entrance is a high school diploma or a certificate of attendance or General Educational Development (GED) certificate.

Open university

An open university is a university with an open-door academic policy, with minimal or no entry requirements. Open universities may employ specific teaching methods, such as open supported learning or distance education. However, not all open universities focus on distance education, nor do distance-education universities necessarily have open admission policies.

Semiconductor intellectual property core

In electronic design a semiconductor intellectual property core, IP core, or IP block is a reusable unit of logic, cell, or integrated circuit (commonly called a "chip") layout design that is the intellectual property of one party. IP cores may be licensed to another party or can be owned and used by a single party alone. The term is derived from the licensing of the patent and/or source code copyright that exist in the design. IP cores can be used as building blocks within application-specific integrated circuit (ASIC) designs or field-programmable gate array (FPGA) logic designs.

Soft microprocessor

A soft microprocessor (also called softcore microprocessor or a soft processor) is a microprocessor core that can be wholly implemented using logic synthesis. It can be implemented via different semiconductor devices containing programmable logic (e.g., ASIC, FPGA, CPLD), including both high-end and commodity variations.Most systems, if they use a soft processor at all, only use a single soft processor. However, a few designers tile as many soft cores onto an FPGA as will fit. In those multi-core systems, rarely used resources can be shared between all the cores in a cluster.

While many people put exactly one soft microprocessor on a FPGA, a sufficiently large FPGA can hold two or more soft microprocessors, resulting in a multi-core processor. The number of soft processors on a single FPGA is limited only by the size of the FPGA. Some people have put dozens or hundreds of soft microprocessors on a single FPGA. This is one way to implement massive parallelism in computing, and can likewise by applied to in-memory computing.

A soft microprocessor and its surrounding peripherals implemented in a FPGA is less vulnerable to obsolescence than a discrete processor.

Wishbone (computer bus)

The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip. The Wishbone Bus is used by many designs in the OpenCores project.

A large number of open-source CPU designs and auxiliary computer peripherals have been released with Wishbone interfaces. Many can be found at OpenCores, a foundation that attempts to make open-source hardware designs available.

Wishbone is intended as a "logic bus". It does not specify electrical information or the bus topology. Instead, the specification is written in terms of "signals", clock cycles, and high and low levels.

This ambiguity is intentional. Wishbone is made to let designers combine several designs written in Verilog, VHDL or some other logic-description language for electronic design automation. Wishbone provides a standard way for designers to combine these hardware logic designs (called "cores").

Wishbone is defined to have 8, 16, 32, and 64-bit buses. All signals are synchronous to a single clock but some slave responses must be generated combinatorially for maximum performance. Wishbone permits addition of a "tag bus" to describe the data. But reset, simple addressed reads and writes, movement of blocks of data, and indivisible bus cycles all work without tags.

Wishbone is open source, which makes it easy for engineers and hobbyists to share public domain designs for hardware logic on the Internet. To prevent preemption of its technologies by aggressive patenting, the Wishbone specification includes examples of prior art, to prove its concepts are in the public domain.

A device does not conform to the Wishbone specification unless it includes a data sheet that describes what it does, bus width, utilization, etc. Promoting reuse of a design requires the data sheet. Making a design reusable in turn makes it easier to share with others.

The Simple Bus Architecture is a simplified version of the Wishbone specification.

Zet (hardware)

Zet is a clone x86 processor where its machine code compatible with x86 processors developed as an effort to make open-hardware processor.

The hardware design can be synthesized in a configurable device such an FPGA, CPLD, or on custom ASIC, and is considered as SoCAs of now, the project only supports 16-bit and able to run DOS-compatible or Windows 3.x operating systems.

There has been no activity in the Zet project since 2013.

Concepts and
Projects and

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