The nanometre (International spelling as used by the International Bureau of Weights and Measures; SI symbol: nm) or nanometer (American spelling) is a unit of length in the metric system, equal to one billionth (short scale) of a metre (0.000000001 m). The name combines the SI prefix nano- (from the Ancient Greek νάνος, nanos, "dwarf") with the parent unit name metre (from Greek μέτρον, metrοn, "unit of measurement"). It can be written in scientific notation as 1×10−9 m, in engineering notation as 1 E−9 m, and as simply 1/ metres. When used as a prefix for something other than a unit of measure (as in "nanoscience"), nano refers to nanotechnology, or phenomena typically occurring on a scale of nanometres (see nanoscopic scale).
The nanometre is often used to express dimensions on an atomic scale: the diameter of a helium atom, for example, is about 0.06 nm, and that of a ribosome is about 20 nm. The nanometre is also commonly used to specify the wavelength of electromagnetic radiation near the visible part of the spectrum: visible light ranges from around 400 to 700 nm. The ångström, which is equal to 0.1 nm, was formerly used for these purposes, but is still used in other fields.
Since the late 1980s, in usages such as the 32 nm and the 22 nm semiconductor node, it has also been used to describe typical feature sizes in successive generations of the ITRS Roadmap for miniaturization in the semiconductor industry.
|1 nm in ...||... is equal to ...|
|SI units|| 1×10−9 m|
|Natural units|| 6.1877×1025 ℓP|
|imperial/US units|| 3.2808×10−9 ft|
The nanometre was formerly known as the millimicrometre – or, more commonly, the millimicron for short – since it is 1/ of a micron (micrometre), and was often denoted by the symbol mµ or (more rarely and confusingly, since it logically should refer to a millionth of a micron) as µµ.
In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nanometer (10 nm) node as the technology node following the 14 nm node. "10 nm class" denotes chips made using process technologies between 10 and 20 nanometers.
All production "10 nm" processes are based on silicon CMOS finFET technology. Samsung first started their production of "10 nm" class chips in 2013 for their multi-level cell (MLC) flash memory chips, followed by other products in 2016, and then for the Galaxy S8 in 2017. TSMC began commercial production of 10 nm chips in 2016, and Intel later began production of 10 nm chips in 2018.
The 10 nm process from Intel is similar to the 7 nm processes offered by Samsung and TSMC, thus some argue that what really matters beyond 10 nm is transistor density (number of transistors per square milimeter).130 nanometer
The 130 nanometer (130 nm) process refers to the level of semiconductor process technology that was reached around the 2001 timeframe, by leading semiconductor companies like Fujitsu, Intel, Texas Instruments, IBM, and TSMC.
The origin of the 130 nm value is historical, as it reflects a trend of 70% scaling every 2–3 years. The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS).
Some of the first CPUs manufactured with this process include Intel Tualatin family of Pentium III processors.14 nanometer
The 14 nanometer (14 nm) technology node is the successor to the 22 nm/(20 nm) node. The 14 nm was so named by the International Technology Roadmap for Semiconductors (ITRS). One nanometer (nm) is one billionth of a meter. Until about 2011, the node following 22 nm was expected to be 16 nm. All 14 nm nodes use FinFET technology.
In 2013, SK Hynix began mass-production of 16 nm NAND flash, TSMC began 16 nm FinFET production, and Samsung began 10 nm class NAND flash production. Intel began shipping 14 nm scale devices to consumers in 2014.180 nanometer
The 180 nanometer (180 nm) process refers to the level of semiconductor process technology that was reached around the 1998–2000 timeframe by leading semiconductor companies like TSMC, Fujitsu, Sony, Toshiba, Intel, AMD, Texas Instruments and IBM.
The origin of the 180 nm value is historical, as it reflects a trend of 70% scaling every 2–3 years. The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS).
Some of the first CPUs manufactured with this process include Intel Coppermine family of Pentium III processors. This was the first technology using a gate length shorter than that of light used for lithography (which has a minimum of 193 nm).
Some more recent microprocessors and microcontrollers (e.g. PIC) are using this technology because it is typically low cost and does not require upgrading of existing equipment.22 nanometer
The 22 nanometer (22 nm) node is the process step following the 32 nm in CMOS semiconductor device fabrication. The typical half-pitch (i.e., half the distance between identical features in an array) for a memory cell using the process is around 22 nm. It was first demonstrated by semiconductor companies for use in RAM memory in 2008. In 2010, Toshiba began shipping 24 nm flash memory chips, and Samsung Electronics began mass-producing 20 nm flash memory chips. The first consumer-level CPU deliveries using a 22 nm process started in April 2012.
The ITRS 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5 nm (about twice the diameter of a silicon atom), which is the expected value at the 22 nm node. This is an indication that CMOS scaling in this area has reached a wall at this point, possibly disturbing Moore's law.
20 nanometer is an intermediate half-node die shrink based on the 22 nanometer process.
TSMC began mass production of 20 nm nodes in 2014. The 22 nm process was superseded by commercial 14 nm technology in 2014.250 nanometer
The 250 nanometer (250 nm or 0.25 µm) process refers to a level of semiconductor process technology that was reached by manufacturers around the 1996–1998 timeframe.32 nanometer
The 32 nanometer (32 nm) node is the step following the 45 nanometer process in CMOS semiconductor device fabrication. "32 nanometer" refers to the average half-pitch (i.e., half the distance between identical features) of a memory cell at this technology level. Toshiba produced commercial 32 Gb NAND flash memory chips with the 32 nm process in 2009. Intel and AMD produced commercial microchips using the 32 nanometer process in the early 2010s. IBM and the Common Platform also developed a 32 nm high-κ metal gate process. Intel began selling its first 32 nm processors using the Westmere architecture on 7 January 2010.
28 nanometer was an intermediate half-node die shrink based on the 32 nanometer process.
The 32 nm process was superseded by commercial 22 nm technology in 2012.350 nanometer
The 350 nanometer (350 nm) process refers to the level of semiconductor process technology that was reached around the 1994–1996 timeframe, by leading semiconductor companies like Sony, Intel and IBM.45 nanometer
Per the International Technology Roadmap for Semiconductors, the 45 nanometer (45 nm) technology node should refer to the average half-pitch of a memory cell manufactured at around the 2007–2008 time frame.
Matsushita and Intel started mass-producing 45 nm chips in late 2007, and AMD started production of 45 nm chips in late 2008, while IBM, Infineon, Samsung, and Chartered Semiconductor have already completed a common 45 nm process platform. At the end of 2008, SMIC was the first China-based semiconductor company to move to 45 nm, having licensed the bulk 45 nm process from IBM. In 2008, TSMC moved on to a 40 nm process.
Many critical feature sizes are smaller than the wavelength of light used for lithography (i.e., 193 nm and 248 nm). A variety of techniques, such as larger lenses, are used to make sub-wavelength features. Double patterning has also been introduced to assist in shrinking distances between features, especially if dry lithography is used. It is expected that more layers will be patterned with 193 nm wavelength at the 45 nm node. Moving previously loose layers (such as Metal 4 and Metal 5) from 248 nm to 193 nm wavelength is expected to continue, which will likely further drive costs upward, due to difficulties with 193 nm photoresists.600 nanometer
The 600 nanometer (600 nm) process refers to the level of semiconductor process technology that was reached around the 1990–1995 timeframe, by leading semiconductor companies like Mitsubishi Electric, Toshiba, NEC, Intel and IBM.65-nanometer process
The 65-nanometer (65 nm) process is advanced lithographic node used in volume CMOS semiconductor fabrication. Printed linewidths (i.e., transistor gate lengths) can reach as low as 25 nm on a nominally 65 nm process, while the pitch between two lines may be greater than 130 nm. For comparison, cellular ribosomes are about 20 nm end-to-end. A crystal of bulk silicon has a lattice constant of 0.543 nm, so such transistors are on the order of 100 atoms across. Toshiba and Sony announced the 65nm process in 2002, before Fujitsu and Toshiba began production in 2004, and then TSMC began production in 2005. By September 2007, Intel, AMD, IBM, UMC and Chartered were also producing 65 nm chips.
While feature sizes may be drawn as 65 nm or less, the wavelengths of light used for lithography are 193 nm and 248 nm. Fabrication of sub-wavelength features requires special imaging technologies, such as optical proximity correction and phase-shifting masks. The cost of these techniques adds substantially to the cost of manufacturing sub-wavelength semiconductor products, with the cost increasing exponentially with each advancing technology node. Furthermore, these costs are multiplied by an increasing number of mask layers that must be printed at the minimum pitch, and the reduction in yield from printing so many layers at the cutting edge of the technology. For new integrated-circuit designs, this factors into the costs of prototyping and production.
Gate thickness, another important dimension, is reduced to as little as 1.2 nm (Intel). Only a few atoms insulate the "switch" part of the transistor, causing charge to flow through it. This undesired effect, leakage, is caused by quantum tunneling. The new chemistry of high-κ gate dielectrics must be combined with existing techniques, including substrate bias and multiple threshold voltages, to prevent leakage from prohibitively consuming power.
IEDM papers from Intel in 2002, 2004, and 2005 illustrate the industry trend that the transistor sizes can no longer scale along with the rest of the feature dimensions (gate width only changed from 220 nm to 210 nm going from 90 nm to 65 nm technologies). However, the interconnects (metal and poly pitch) continue to shrink, thus reducing chip area and chip cost, as well as shortening the distance between transistors, leading to higher-performance devices of greater complexity when compared with earlier nodes.800 nanometer
The 800 nanometer (800 nm) process refers to the level of semiconductor process technology that was reached around the 1987–1990 timeframe, by leading semiconductor companies like NTT, NEC, Toshiba, IBM, Hitachi, Matsushita, Mitsubishi Electric and Intel.90 nanometer
The 90 nanometer (90 nm) process refers to the level of CMOS process technology that was reached by the 2003–2005 timeframe, by leading semiconductor companies like Toshiba, Sony, Samsung, Fujitsu, TSMC, IBM, Elpida, Intel, AMD, Infineon, Texas Instruments and Micron Technology.
The origin of the 90 nm value is historical, as it reflects a trend of 70% scaling every 2–3 years. The 90 nm process was developed by Toshiba, Sony and Samsung during 2001–2002, before being introduced in 2002 for Toshiba's eDRAM and Samsung's 2 Gb NAND flash memory, and then produced by Fujitsu in 2003 and TSMC in 2004. The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS).
The 193 nm wavelength was introduced by many (but not all) companies for lithography of critical layers mainly during the 90 nm node. Yield issues associated with this transition (due to the use of new photoresists) were reflected in the high costs associated with this transition.
Even more significantly, the 300 mm wafer size became mainstream at the 90 nm node. The previous wafer size was 200 mm diameter.
Gurtej Singh Sandhu of Micron Technology initiated the development of atomic layer deposition high-k films for DRAM memory devices. This helped drive cost-effective implementation of semiconductor memory, starting with 90-nm node DRAM.Angstrom
The angstrom (, ; ANG-strəm, ANG-strum) or ångström is a unit of length equal to 10−10 m; that is, one ten-billionth of a metre, 0.1 nanometre, or 100 picometres. Its symbol is Å, a letter of the Swedish alphabet.
The angstrom is not a part of the SI system of units, but it can be considered part of the metric system. While deprecated by the IBWM and the NIST, the unit is still often used in the natural sciences and technology to express sizes of atoms, molecules, microscopic biological structures, and lengths of chemical bonds, arrangement of atoms in crystals, wavelengths of electromagnetic radiation, and dimensions of integrated circuit parts. The atomic (covalent) radii of phosphorus, sulfur, and chlorine are about 1 angstrom, while that of hydrogen is about 0.5 angstrom. Visible light has wavelengths in the range of 4000–7000 Å.
The unit is named after the nineteenth-century Swedish physicist Anders Jonas Ångström (Swedish: [²ɔŋːstrœm]). The IBWM and the NIST spell it as ångström; however, this spelling is rare in English texts and not even recorded in some popular US dictionaries. The symbol should always be "Å", no matter how the unit is spelled; but "A" may occur in less formal contexts or typographically limited media.Darwin (spacecraft)
Darwin was a suggested ESA Cornerstone mission which would have involved a constellation of four to nine spacecraft designed to directly detect Earth-like planets orbiting nearby stars and search for evidence of life on these planets. The most recent design envisaged three free-flying space telescopes, each three to four metres in diameter, flying in formation as an astronomical interferometer. These telescopes were to redirect light from distant stars and planets to a fourth spacecraft, which would have contained the beam combiner, spectrometers, and cameras for the interferometer array, and which would have also acted as a communications hub. There was also an earlier design, called the "Robin Laurance configuration," which included six 1.5 metre telescopes, a beam combiner spacecraft, and a separate power and communications spacecraft.The study of this proposed mission ended in 2007 with no further activities planned. To produce an image, the telescopes would have had to operate in formation with distances between the telescopes controlled to within a few micrometres, and the distance between the telescopes and receiver controlled to within about one nanometre. Several more detailed studies would have been needed to determine whether technology capable of such precision is actually feasible.Lamina lucida
The lamina lucida is a component of the basement membrane which is found between the epithelium and underlying connective tissue (e.g., epidermis and dermis of the skin). It is a roughly 40 nanometre wide electron-lucent zone between the plasma membrane of the basal cells and the (electron-dense) lamina densa of the basement membrane.Similarly, electron-lucent and electron-dense zones can be seen between enamel of teeth and the junctional epithelium. The electron-lucent zone is adjacent to the cells of the junctional epithelium and might be considered a continuation of the lamina lucida as both are seen to harbour hemidesmosomes. However, unlike the lamina densa, the electron-dense zone adjacent to enamel show no signs of hemidesmosomes.Some theorize that the lamina lucida is an artifact created when preparing the tissue, and that the lamina lucida is therefore equal to the lamina densa in vivo.Nanoengineering
Nanoengineering is the practice of engineering on the nanoscale. It derives its name from the nanometre, a unit of measurement equalling one billionth of a meter.
Nanoengineering is largely a synonym for nanotechnology, but emphasizes the engineering rather than the pure science aspects of the field.Picometre
The picometre (international spelling as used by the International Bureau of Weights and Measures; SI symbol: pm) or picometer (American spelling) is a unit of length in the metric system, equal to 1×10−12 m, or one trillionth (1/1000000000000) of a metre, which is the SI base unit of length.
The picometre is one thousandth (1/1000 × nm) of a nanometre, one millionth of a micrometre (also known as a micron), and used to be called micromicron, stigma, or bicron. The symbol µµ was once used for it. It is also one hundredth of an Ångström, an internationally recognised (but non-SI) unit of length.Radiant flux
In radiometry, radiant flux or radiant power is the radiant energy emitted, reflected, transmitted or received, per unit time, and spectral flux or spectral power is the radiant flux per unit frequency or wavelength, depending on whether the spectrum is taken as a function of frequency or of wavelength. The SI unit of radiant flux is the watt (W), that is the joule per second (J/s) in SI base units, while that of spectral flux in frequency is the watt per hertz (W/Hz) and that of spectral flux in wavelength is the watt per metre (W/m)—commonly the watt per nanometre (W/nm).
From smallest to largest (left to right). Commonly used units shown in bold italics.