MIPS (Microprocessor without Interlocked Pipelined Stages) is a reduced instruction set computer (RISC) instruction set architecture (ISA):A-1:19 developed by MIPS Computer Systems (an American company that is now called MIPS Technologies).
There are multiple versions of MIPS: including MIPS I, II, III, IV, and V; as well as five releases of MIPS32/64 (for 32- and 64-bit implementations, respectively). The early MIPS architectures were 32-bit only; 64-bit versions were developed later. As of April 2017, the current version of MIPS is MIPS32/64 Release 6. MIPS32/64 primarily differs from MIPS I–V by defining the privileged kernel mode System Control Coprocessor in addition to the user mode architecture.
The MIPS architecture has several optional extensions. MIPS-3D which is a simple set of floating-point SIMD instructions dedicated to common 3D tasks, MDMX (MaDMaX) which is a more extensive integer SIMD instruction set using the 64-bit floating-point registers, MIPS16e which adds compression to the instruction stream to make programs take up less room, and MIPS MT, which adds multithreading capability.
As of April 2017, MIPS processors are used in embedded systems such as residential gateways and routers. Originally, MIPS was designed for general-purpose computing. During the 1980s and 1990s, MIPS processors for personal, workstation, and server computers were used by many companies such as Digital Equipment Corporation, MIPS Computer Systems, NEC, Pyramid Technology, SiCortex, Siemens Nixdorf, Silicon Graphics, and Tandem Computers. Historically, video game consoles such as the Nintendo 64, Sony PlayStation, PlayStation 2, and PlayStation Portable used MIPS processors. MIPS processors also used to be popular in supercomputers during the 1990s, but all such systems have dropped off the TOP500 list. These uses were complemented by embedded applications at first, but during the 1990s, MIPS became a major presence in the embedded processor market, and by the 2000s, most MIPS processors were for these applications. In the mid- to late-1990s, it was estimated that one in three RISC microprocessors produced was a MIPS processor.
MIPS is a modular architecture supporting up to four coprocessors (CP0/1/2/3). In MIPS terminology, CP0 is the System Control Coprocessor (an essential part of the processor that is implementation-defined in MIPS I–V), CP1 is an optional floating-point unit (FPU) and CP2/3 are optional implementation-defined coprocessors (MIPS III removed CP3 and reused its opcodes for other purposes). For example, in the PlayStation video game console, CP2 is the Geometry Transformation Engine (GTE), which accelerates the processing of geometry in 3D computer graphics.
In December 2018, Wave Computing, the new owner of the MIPS architecture (see MIPS Technologies), announced that MIPS ISA will be open-sourced in a program dubbed the MIPS Open initiative. The program being planned for 2019 is intended to open up access to the most recent versions of both the 32-bit and 64-bit designs making them available without any licensing or royalty fees as well as granting participants licenses to existing MIPS patents.
|Designer||MIPS Technologies, Imagination Technologies|
|Bits||64-bit (32 → 64)|
|Version||MIPS32/64 Release 6 (2014)|
|Branching||Compare and branch|
|Page size||4 KB|
|Open||Yes, and royalty free (scheduled for Q1 2019)|
The first version of the MIPS architecture was designed by MIPS Computer Systems for its R2000 microprocessor, the first MIPS implementation. Both MIPS and the R2000 were introduced together in 1985. When MIPS II was introduced, MIPS was renamed MIPS I to distinguish it from the new version.:32
MIPS I has thirty-two 32-bit general-purpose registers (GPR). Register $0 is hardwired to zero and writes to it are discarded. Register $31 is the link register. For integer multiplication and division instructions, which run asynchronously from other instructions, a pair of 32-bit registers, HI and LO, are provided. There is a small set of instructions for copying data between the general-purpose registers and the HI/LO registers.
The program counter has 32 bits. The two low-order bits always contain zero since MIPS I instructions are 32 bits long and are aligned to their natural word boundaries.
Instructions are divided into three types: R, I and J. Every instruction starts with a 6-bit opcode. In addition to the opcode, R-type instructions specify three registers, a shift amount field, and a function field; I-type instructions specify two registers and a 16-bit immediate value; J-type instructions follow the opcode with a 26-bit jump target.:A-174
The following are the three formats used for the core instruction set:
|Type||-31- format (bits) -0-|
|R||opcode (6)||rs (5)||rt (5)||rd (5)||shamt (5)||funct (6)|
|I||opcode (6)||rs (5)||rt (5)||immediate (16)|
|J||opcode (6)||address (26)|
MIPS I has instructions that load and store 8-bit bytes, 16-bit halfwords, and 32-bit words. Only one addressing mode is supported: base + displacement. Since MIPS I is a 32-bit architecture, loading quantities fewer than 32 bits requires the datum to be either signed- or zero-extended to 32 bits. The load instructions suffixed by "unsigned" perform zero extension; otherwise sign extension is performed. Load instructions source the base from the contents of a GPR (rs) and write the result to another GPR (rt). Store instructions source the base from the contents of a GPR (rs) and the store data from another GPR (rt). All load and store instructions compute the memory address by summing the base with the sign-extended 16-bit immediate. MIPS I requires all memory accesses to be aligned to their natural word boundaries, otherwise an exception is signaled. To support efficient unaligned memory accesses, there are load/store word instructions suffixed by "left" or "right". All load instructions are followed by a load delay slot. The instruction in the load delay slot cannot use the data loaded by the load instruction. The load delay slot can be filled with an instruction that is not dependent on the load; a nop is substituted if such an instruction cannot be found.
|Load Word Left||LWL||I||3410||rs||rt||offset|
|Load Byte Unsigned||LBU||I||3610||rs||rt||offset|
|Load Halfword Unsigned||LHU||I||3710||rs||rt||offset|
|Load Word Right||LWR||I||3810||rs||rt||offset|
|Store Word Left||SWL||I||4210||rs||rt||offset|
|Store Word Right||SWR||I||4610||rs||rt||offset|
MIPS I has instructions to perform addition and subtraction. These instructions source their operands from two GPRs (rs and rt), and write the result to a third GPR (rd). Alternatively, addition can source one of the operands from a 16-bit immediate (which is sign-extended to 32 bits). The instructions for addition and subtraction have two variants: by default, an exception is signaled if the result overflows; instructions with the "unsigned" suffix do not signal an exception. The overflow check interprets the result as a 32-bit two's complement integer.
MIPS I has instructions to perform bitwise logical AND, OR, XOR, and NOR. These instructions source their operands from two GPRs and write the result to a third GPR. The AND, OR, and XOR instructions can alternatively source one of the operands from a 16-bit immediate (which is zero-extended to 32 bits).
The Set on relation instructions write one or zero to the destination register if the specified relation is true or false. These instructions source their operands from two GPRs or one GPR and a 16-bit immediate (which is sign-extended to 32 bits), and write the result to a third GPR. By default, the operands are interpreted as signed integers. The variants of these instructions that are suffixed with "unsigned" interpret the operands as unsigned integers (even those that source an operand from the sign-extended 16-bit immediate).
The Load Immediate Upper instruction copies the 16-bit immediate into the high-order 16 bits of a GPR. It is used in conjunction with the Or Immediate instruction to load a 32-bit immediate into a register.
|Set on Less Than||SLT||R||010||rs||rt||rd||010||4210|
|Set on Less Than Unsigned||SLTU||R||010||rs||rt||rd||010||4310|
|Add Immediate Unsigned||ADDIU||I||910||$s||$d||immediate|
|Set on Less Than Immediate||SLTI||I||1010||$s||$d||immediate|
|Set on Less Than Immediate Unsigned||SLTIU||I||1110||$s||$d||immediate|
|Exclusive Or Immediate||XORI||I||1410||$s||$d||immediate|
|Load Upper Immediate||LUI||I||1510||010||$d||immediate|
MIPS I has instructions to perform left and right logical shifts and right arithmetic shifts. The operand is obtained from a GPR (rt), and the result is written to another GPR (rd). The shift distance is obtained from either a GPR (rs) or a 5-bit "shift amount" (the "sa" field).
|Shift Left Logical||SLL||R||010||010||rt||rd||sa||010|
|Shift Right Logical||SRL||R||010||010||rt||rd||sa||210|
|Shift Right Arithmetic||SRA||R||010||010||rt||rd||sa||310|
|Shift Left Logical Variable||SLLV||R||010||rs||rt||rd||010||410|
|Shift Right Logical Variable||SRLV||R||010||rs||rt||rd||010||610|
|Shift Right Arithmetic Variable||SRAV||R||010||rs||rt||rd||010||710|
MIPS I has instructions for signed and unsigned integer multiplication and division. These instructions source their operands from two GPRs and write their results to a pair of 32-bit registers called HI and LO, since they may execute separately from (and concurrently with) the other CPU instructions. For multiplication, the high- and low-order halves of the 64-bit product is written to HI and LO (respectively). For division, the quotient is written to LO and the remainder to HI. To access the results, a pair of instructions (Move from HI and Move from LO) is provided to copy the contents of HI or LO to a GPR. These instructions are interlocked: reads of HI and LO do not proceed past an unfinished arithmetic instruction that will write to HI and LO. Another pair of instructions (Move to HI or Move to LO) copies the contents of a GPR to HI and LO. These instructions are used to restore HI and LO to their original state after exception handling. Instructions that read HI or LO must be separated by two instructions that do not write to HI or LO.
|Move from HI||MFHI||R||010||010||010||rd||010||1610|
|Move to HI||MTHI||R||010||rs||010||010||010||1710|
|Move from LO||MFLO||R||010||010||010||rd||010||1810|
|Move to LO||MTLO||R||010||rs||010||010||010||1910|
All MIPS I control flow instructions are followed by a branch delay slot. Unless the branch delay slot is filled by an instruction performing useful work, an nop is substituted. MIPS I branch instructions compare the contents of a GPR (rs) against zero or another GPR (rt) as signed integers and branch if the specified condition is true. Control is transferred to the address computed by shifting the 16-bit offset left by two bits, sign-extending the 18-bit result, and adding the 32-bit sign-extended result to the sum of the program counter (instruction address) and 810. Jumps have two versions: absolute and register-indirect. Absolute jumps ("Jump" and "Jump and Link") compute the address control is transferred to by shifting the 26-bit instr_index left by two bits and concatenating the 28-bit result with the four high-order bits of the address of the instruction in the branch delay slot. Register-indirect jumps transfer control to the instruction at the address sourced from a GPR (rs). The address sourced from the GPR must be word-aligned, else an exception is signaled after the instruction in the branch delay slot is executed. Branch and jump instructions that link (except for "Jump and Link Register") save the return address to GPR 31. The "Jump and Link Register" instruction permits the return address to be saved to any writable GPR.
|Jump and Link Register||JALR||R||010||rs||010||rd||010||910|
|Branch on Less Than Zero||BLTZ||I||110||rs||010||offset|
|Branch on Greater Than or Equal to Zero||BGEZ||I||110||rs||110||offset|
|Branch on Less Than Zero and Link||BLTZAL||I||110||rs||16||offset|
|Branch on Greater Than or Equal to Zero and Link||BGEZAL||I||110||rs||17||offset|
|Jump and Link||JAL||J||310||instr_index|
|Branch on Equal||BEQ||I||410||rs||rt||offset|
|Branch on Not Equal||BNE||I||510||rs||rt||offset|
|Branch on Less Than or Equal to Zero||BLEZ||I||610||rs||010||offset|
|Branch on Greater Than Zero||BGTZ||I||710||rs||010||offset|
MIPS I has two instructions for software to signal an exception: System Call and Breakpoint. System Call is used by user mode software to make kernel calls; and Breakpoint is used to transfer control to a debugger via the kernel's exception handler. Both instructions have a 20-bit Code field that can contain operating environment-specific information for the exception handler.
MIPS has 32 floating-point registers. Two registers are paired for double precision numbers. Odd numbered registers cannot be used for arithmetic or branching, just as part of a double precision register pair, resulting in 16 usable registers for most instructions (moves/copies and loads/stores were not affected).
|Floating-Point Add||add.s $x,$y,$z||$x = $y + $z||1710||010||$z||$y||$x||010|
|Floating-Point Subtract||sub.s $x,$y,$z||$x = $y - $z||1710||010||$z||$y||$x||110|
|Floating-Point Multiply||mul.s $x,$y,$z||$x = $y * $z||1710||010||$z||$y||$x||210|
|Floating-Point Divide||div.s $x,$y,$z||$x = $y / $z||1710||010||$z||$y||$x||310|
|Floating-Point Add||add.d $x,$y,$z||$x = $y + $z||1710||110||$z||$y||$x||010|
|Floating-Point Subtract||sub.d $x,$y,$z||$x = $y - $z||1710||110||$z||$y||$x||110|
|Floating-Point Multiply||mul.d $x,$y,$z||$x = $y * $z||1710||110||$z||$y||$x||210|
|Floating-Point Divide||div.d $x,$y,$z||$x = $y / $z||1710||110||$z||$y||$x||310|
|Floating-Point Compare (eq,ne,lt,le,gt,ge)||c.lt.s $f2,$f4||cond = ($f2 < $f4)|
|Floating-Point Compare (eq,ne,lt,le,gt,ge)||c.lt.d $f2,$f4||cond = ($f2 < $f4)|
Single precision is denoted by the .s suffix, while double precision is denoted by the .d suffix.
|Load word coprocessor||lwcZ $x,CONST ($y)||Coprocessor[Z].DataRegister[$x] = Memory[$y + CONST]||I||Loads the 4 byte word stored from: MEM[$y+CONST] into a Coprocessor data register. Sign extension.|
|Store word coprocessor||swcZ $x,CONST ($y)||Memory[$y + CONST] = Coprocessor[Z].DataRegister[$x]||I||Stores the 4 byte word held by a Coprocessor data register into: MEM[$y+CONST]. Sign extension.|
|Branch on FP True||bc1t 100||
if (cond) goto PC+4+100;
|PC relative branch if FP condition|
|Branch on FP False||bc1f 100||
if (!cond) goto PC+4+100;
|PC relative branch if not condition|
MIPS II removed the load delay slot:41 and added several sets of instructions. For shared-memory multiprocessing, the Synchronize Shared Memory, Load Linked Word, and Store Conditional Word instructions were added. A set of Trap-on-Condition instructions were added. These instructions caused an exception if the evaluated condition is true. All existing branch instructions were given branch-likely versions that executed the instruction in the branch delay slot only if the branch is taken.:40 These instructions improve performance in certain cases by allowing useful instructions to fill the branch delay slot.:212 Doubleword load and store instructions for COP1–3 were added. Consistent with other memory access instructions, these loads and stores required the doubleword to be naturally aligned.
The instruction set for the floating point coprocessor also had several instructions added to it. An IEEE 754-compliant floating-point square root instruction was added. It supported both single- and double-precision operands. A set of instructions that converted single- and double-precision floating-point numbers to 32-bit words were added. These complemented the existing conversion instructions by allowing the IEEE rounding mode to be specified by the instruction instead of the Floating Point Control and Status Register.
MIPS Computer Systems' R6000 microprocessor (1989) is the first MIPS II implementation.:8 Designed for servers, the R6000 was fabricated and sold by Bipolar Integrated Technology, but was a commercial failure. During the mid-1990s, many new 32-bit MIPS processors for embedded systems were MIPS II implementations because the introduction of the 64-bit MIPS III architecture in 1991 left MIPS II as the newest 32-bit MIPS architecture until MIPS32 was introduced in 1999.A:19
|Synchronize Shared Memory||SYNC|
|Trap if Greater Than or Equal||TGE|
|Trap if Greater Than or Equal Unsigned||TGEU|
|Trap if Less Than||TLT|
|Trap if Less Than Unsigned||TLTU|
|Trap if Equal||TEQ|
|Trap if Not Equal||TNE|
|Branch on Less Than or Equal to Zero Likely||BLEZL|
|Branch on Greater Than or Equal to Zero Likely||BGEZL|
|Trap if Greater Than or Equal Immediate||TGEI|
|Trap if Greater Than or Equal Unsigned Immediate||TGEIU|
|Trap if Less Than Immediate||TLTI|
|Trap if Less Than Unsigned Immediate||TLTIU|
|Trap if Equal Immediate||TEQI|
|Trap if Not Equal Immediate||TNEI|
|Branch on Less Than Zero and Link Likely||BLTZALL|
|Branch on Greater Than or Equal to Zero and Link Likely||BGEZAL|
|Floating-Point Square Root||SQRT.S|
|Floating-Point Square Root||SQRT.D|
|Floating-Point Round to Word Fixed-Point||ROUND.S|
|Floating-Point Round to Word Fixed-Point||ROUND.D|
|Floating-Point Truncate to Word Fixed-Point||TRUNC.S|
|Floating-Point Truncate to Word Fixed-Point||TRUNC.D|
|Floating-Point Ceiling to Word Fixed-Point||CEIL.S|
|Floating-Point Ceiling to Word Fixed-Point||CEIL.D|
|Floating-Point Ceiling to Word Fixed-Point||FLOOR.S|
|Floating-Point Ceiling to Word Fixed-Point||FLOOR.D|
|Branch on FP False Likely||BC1FL|
|Branch on FP True Likely||BC1TL|
|Branch on Equal Likely||BEQL|
|Branch on Not Equal Likely||BNEL|
|Branch on Less Than Zero Likely||BLTZL|
|Branch on Greater Than Zero Likely||BGTZL|
|Load Doubleword to Coprocessor 1||LDC1|
|Load Doubleword to Coprocessor 2||LDC2|
|Load Doubleword to Coprocessor 3||LDC3|
|Store Doubleword to Coprocessor 1||SDC1|
|Store Doubleword to Coprocessor 2||SDC2|
|Store Doubleword to Coprocessor 3||SDC3|
MIPS III is a backwards-compatible extension of MIPS II that added support for 64-bit memory addressing and integer operations. The 64-bit data type is called a doubleword, and MIPS III extended the general-purpose registers, HI/LO registers, and program counter to 64 bits to support it. New instructions were added to load and store doublewords, to perform integer addition, subtraction, multiplication, division, and shift operations on them, and to move doubleword between the GPRs and HI/LO registers. Existing instructions originally defined to operate on 32-bit words were redefined, where necessary, to sign-extend the 32-bit results to permit words and doublewords to be treated identically by most instructions. Among those instructions redefined was Load Word. In MIPS III it sign-extends words to 64 bits. To complement Load Word, a version that zero-extends was added.
The R instruction format's inability to specify the full shift distance for 64-bit shifts (its 5-bit shift amount field is too narrow to specify the shift distance for doublewords) required MIPS III to provide three 64-bit versions of each MIPS I shift instruction. The first version is a 64-bit version of the original shift instructions, used to specify constant shift distances of 0–31 bits. The second version is similar to the first, but adds 3210 the shift amount field's value so that constant shift distances of 32–64 bits can be specified. The third version obtains the shift distance from the six low-order bits of a GPR.
MIPS III added a supervisor privilege level in between the existing kernel and user privilege levels. This feature only affected the implementation-defined System Control Processor (Coprocessor 0).
|Doubleword Shift Left Logical Variable||DSLLV||R||010||rs||rt||rd||010||2010|
|Doubleword Shift Right Logical Variable||DSRLV||R||010||rs||rt||rd||010||2210|
|Doubleword Shift Right Arithmetic Variable||DSRAV||R||010||rs||rt||rd||010||2310|
|Doubleword Multiply Unsigned||DMULTU||R||010||rs||rt||010||010||2910|
|Doubleword Divide Unsigned||DDIVU||R||010||rs||rt||010||010||3110|
|Doubleword Add Unsigned||DADDU||R||010||rs||rt||rd||010||4510|
|Doubleword Subtract Unsigned||DSUBU||R||010||rs||rt||rd||010||4710|
|Doubleword Shift Left Logical||DSLL||R||010||010||rt||rd||sa||5610|
|Doubleword Shift Right Logical||DSRL||R||010||010||rt||rd||sa||5810|
|Doubleword Shift Right Arithmetic||DSRA||R||010||010||rt||rd||sa||5910|
|Doubleword Shift Left Logical + 32||DSLL32||R||010||010||rt||rd||sa||6010|
|Doubleword Shift Right Logical + 32||DSRL32||R||010||010||rt||rd||sa||6210|
|Doubleword Shift Right Logical + 32||DSRL32||R||010||010||rt||rd||sa||6310|
|Doubleword Add Immediate||DADDI||I||2410||rs||rd||immediate|
|Doubleword Add Immediate Unsigned||DADDIU||I||2510||rs||rd||immediate|
|Load Doubleword Left||LDL||I||2610||rs||rt||offset|
|Load Doubleword Right||LDR||I||2710||rs||rt||offset|
|Load Word Unsigned||LWU||I||3910||rs||rt||offset|
|Store Doubleword Left||SDL||I||4410||rs||rt||offset|
|Store Doubleword Right||SDR||I||4510||rs||rt||offset|
MIPS III removed the Coprocessor 3 (CP3) support instructions, and reused its opcodes for the new doubleword instructions. The remaining coprocessors gained instructions to move doublewords between coprocessor registers and the GPRs. The floating general registers (FGRs) were extended to 64 bits and the requirement for instructions to use even-numbered register only was removed. This is incompatible with earlier versions of the architecture; a bit in the floating-point control/status register is used to operate the MIPS III floating-point unit (FPU) in a MIPS I- and II-compatible mode. The floating-point control registers were not extended for compatibility. The only new floating-point instructions added were those to copy doublewords between the CPU and FPU convert single- and double-precision floating-point numbers into doubleword integers and vice versa.
|Doubleword Move To Coprocessor 1||DMFC1||R||1710||110||rt||fs||010||010|
|Doubleword Move To Coprocessor 1||DMTC1||R||1710||510||rt||fs||010||010|
|Floating Point Round to Long||ROUND.L.S||R||1710||1610||010||fs||fd||8|
|Floating Point Round to Long||ROUND.L.D||R||1710||1710||010||fs||fd||810|
|Floating Point Truncate to Long||TRUNC.L.S||R||1710||1610||010||fs||fd||910|
|Floating Point Truncate to Long||TRUNC.L.D||R||1710||1710||010||fs||fd||910|
|Floating Point Ceiling to Long||CEIL.L.S||R||1710||1610||010||fs||fd||1010|
|Floating Point Ceiling to Long||CEIL.L.D||R||1710||1710||010||fs||fd||1010|
|Floating Point Floor to Long||FLOOR.L.S||R||1710||1610||0||fs||fd||1110|
|Floating Point Floor to Long||FLOOR.L.D||R||1710||1710||010||fs||fd||1110|
|Floating Point Convert to Single||CVT.S.L||R||1710||1610||010||fs||fd||3210|
|Floating Point Convert to Double||CVT.D.L||R||1710||1710||010||fs||fd||3310|
|Floating Point Convert to Long||CVT.L.S||R||1710||1610||010||fs||fd||3710|
|Floating Point Convert to Long||CVT.L.D||R||1710||1710||010||fs||fd||3710|
MIPS Computer Systems' R4000 microprocessor (1991) was the first MIPS III implementation. It was designed for use in personal, workstation, and server computers. MIPS Computer Systems aggressively promoted the MIPS architecture and R4000, establishing the Advanced Computing Environment (ACE) consortium to advance its Advanced RISC Computing (ARC) standard, which aimed to establish MIPS as the dominant personal computing platform. ARC found little success in personal computers, but the R4000 (and the R4400 derivative) were widely used in workstation and server computers, especially by its largest user, Silicon Graphics. Other uses of the R4000 included high-end embedded systems and supercomputers.
MIPS III was eventually implemented by a number of embedded microprocessors. Quantum Effect Design's R4600 (1993) and its derivatives was widely used in high-end embedded systems and low-end workstations and servers. MIPS Technologies' R4200 (1994), was designed for embedded systems, laptop, and personal computers. A derivative, the R4300i, fabricated by NEC Electronics, was used in the Nintendo 64 game console. The Nintendo 64, along with the PlayStation, were among the highest volume users of MIPS architecture processors in the mid-1990s.
MIPS IV is the fourth version of the architecture. It is a superset of MIPS III and is compatible with all existing versions of MIPS. MIPS IV was designed to mainly improve floating-point (FP) performance. To improve access to operands, an indexed addressing mode (base + index, both sourced from GPRs) for FP loads and stores was added, as were prefetch instructions for performing memory prefetching and specifying cache hints (these supported both the base + offset and base + index addressing modes).
MIPS IV added several features to improve instruction-level parallelism. To alleviate the bottleneck caused by a single condition bit, seven condition code bits were added to the floating-point control and status register, bringing the total to eight. FP comparison and branch instructions were redefined so they could specify which condition bit was written or read (respectively); and the delay slot in between an FP branch that read the condition bit written to by a prior FP comparison was removed. Support for partial predication was added in the form of conditional move instructions for both GPRs and FPRs; and an implementation could choose between having precise or imprecise exceptions for IEEE 754 traps.
MIPS IV added several new FP arithmetic instructions for both single- and double-precision FPNs: fused-multiply add or subtract, reciprocal, and reciprocal square-root. The FP fused-multiply add or subtract instructions perform either one or two roundings (it is implementation-defined), to exceed or meet IEEE 754 accuracy requirements (respectively). The FP reciprocal and reciprocal square-root instructions do not comply with IEEE 754 accuracy requirements, and produce results that differ from the required accuracy by one or two units of last place (it is implementation defined). These instructions serve applications where instruction latency is more important than accuracy.
The first MIPS IV implementation was the MIPS Technologies R8000 microprocessor chipset (1994). The design of the R8000 began at Silicon Graphics, Inc. and it was only used in high-end workstations and servers for scientific and technical applications where high performance on large floating-point workloads was important. Later implementations were the MIPS Technologies R10000 (1996) and the Quantum Effect Devices R5000 (1996) and RM7000 (1998). The R10000, fabricated and sold by NEC Electronics and Toshiba, and its derivatives were used by NEC, Pyramid Technology, Silicon Graphics, Inc., and Tandem Computers (among others) in workstations, servers, and supercomputers. The R5000 and R7000 found use in high-end embedded systems, personal computers, and low-end workstations and servers. A derivative of the R5000 from Toshiba, the R5900, was used in Sony Computer Entertainment's Emotion Engine, which powered its PlayStation 2 game console.
Announced on October 21, 1996 at the Microprocessor Forum 1996 alongside the MIPS Digital Media Extensions (MDMX) extension, MIPS V was designed to improve the performance of 3D graphics transformations. In the mid-1990s, a major use of non-embedded MIPS microprocessors were graphics workstations from SGI. MIPS V was completed by the integer-only MDMX extension to provide a complete system for improving the performance of 3D graphics applications.
MIPS V implementations were never introduced. On May 12, 1997, SGI announced the "H1" ("Beast") and "H2" ("Capitan") microprocessors. The former was to have been the first MIPS V implementation, and was due to be introduced in the first half of 1999. The "H1" and "H2" projects were later combined and were eventually canceled in 1998. While there have not been any MIPS V implementations, MIPS64 Release 1 (1999) was based on MIPS V and retains all of its features as an optional Coprocessor 1 (FPU) feature called Paired-Single.
MIPS V added a new data type, the Paired Single (PS), which consisted of two single-precision (32-bit) floating-point numbers stored in the existing 64-bit floating-point registers. Variants of existing floating-point instructions for arithmetic, compare and conditional move were added to operate on this data type in a SIMD fashion. New instructions were added for loading, rearranging and converting PS data.:426–429 It was the first instruction set to exploit floating-point SIMD with existing resources.
When MIPS Technologies was spun-out of Silicon Graphics in 1998, it refocused on the embedded market. Up to MIPS V, each successive version was a strict superset of the previous version, but this property was found to be a problem, and the architecture definition was changed to define a 32-bit and a 64-bit architecture: MIPS32 and MIPS64. Both were introduced in 1999. MIPS32 is based on MIPS II with some additional features from MIPS III, MIPS IV, and MIPS V; MIPS64 is based on MIPS V. NEC, Toshiba and SiByte (later acquired by Broadcom) each obtained licenses for MIPS64 as soon as it was announced. Philips, LSI Logic, IDT, Raza Microelectronics, Inc., Cavium, Loongson Technology and Ingenic Semiconductor have since joined them.
The first release of MIPS32, based on MIPS II, added conditional moves, prefetch instructions, and other features from the R4000 and R5000 families of 64-bit processors. The first release of MIPS64 adds a MIPS32 mode to run 32-bit code. The MUL and MADD (multiply-add) instructions, previously available in some implementations, were added to the MIPS32 and MIPS64 specifications, as were cache control instructions.
MIPS32/MIPS64 Release 6 in 2014 added the following:
Removed infrequently used instructions:
Reorganized the instruction encoding, freeing space for future expansions.
The microMIPS32/64 architectures are supersets of the MIPS32 and MIPS64 architectures (respectively) designed to replace the MIPS16e ASE. A disadvantage of MIPS16e is that it requires a mode switch before any of its 16-bit instructions can be processed. microMIPS adds versions of the most-frequently used 32-bit instructions that are encoded as 16-bit instructions. This allows programs to intermix 16- and 32-bit instructions without having to switch modes. microMIPS was introduced alongside of MIPS32/64 Release 3, and each subsequent release of MIPS32/64 has a corresponding microMIPS32/64 version. A processor may implement microMIPS32/64 or both microMIPS32/64 and its corresponding MIPS32/64 subset. Starting with MIPS32/64 Release 6, support for MIPS16e ended, and microMIPS is the only form of code compression in MIPS.
The base MIPS32 and MIPS64 architectures can be supplemented with a number of optional architectural extensions, which are collectively referred to as application-specific extensions (ASEs). These ASEs provide features that improve the efficiency and performance of certain workloads, such as digital signal processing.
Enhancements for microcontroller applications. The MCU ASE (application-specific extension) has been developed to extend the interrupt controller support, reduce the interrupt latency and enhance the I/O peripheral control function typically required in microcontroller system designs.
MIPS16 is an Application-Specific Extension for MIPS I through to V designed by LSI Logic and MIPS Technologies, announced on October 21, 1996 alongside its first implementation, the LSI Logic TinyRISC processor. MIPS16 was subsequently licensed by NEC Electronics, Philips Semiconductors, and Toshiba (among others); and implemented as an extension to the MIPS I, II, an III architectures. MIPS16 decreases the size of application by up to 40% by using 16-bit instructions instead of 32-bit instructions' and also improves power efficiency, the instruction cache hit rate, and is equivalent in performance to its base architecture. It is supported by hardware and software development tools from MIPS Technologies and other providers.
MIPS16e is an improved version of MIPS16 first supported by MIPS32 and MIPS64 Release 1.
MIPS16e2 is an improved version of MIPS16 that is supported by MIPS32 and MIPS64 (up to Release 5). Release 6 replaced it with microMIPS.
The DSP ASE is an optional extension to the MIPS32/MIPS64 Release 2 and newer instruction sets which can be used to accelerate a large range of "media" computations—particularly audio and video. The DSP module comprises a set of instructions and state in the integer pipeline and requires minimal additional logic to implement in MIPS processor cores. Revision 2 of the ASE was introduced in the second half of 2006. This revision adds extra instructions to the original ASE, but is otherwise backwards-compatible with it.
Unlike the bulk of the MIPS architecture, it's a fairly irregular set of operations, many chosen for a particular relevance to some key algorithm.
Its main novel features (vs original MIPS32):
To make use of MIPS DSP ASE, you may:
-ftree-vectorize. The advantage of auto-vectorization is that the compiler can recognize scalar variables (which can be integer, fixed-point, or floating-point types) in order to utilize SIMD instructions automatically. In the ideal case, when auto-vectorization is used, there is no need to use SIMD variables explicitly.
Linux 2.6.12-rc5 starting 2005-05-31 adds support for the DSP ASE. Note that to actually make use of the DSP ASE a toolchain which support this is required. GCC already has support for DSP and DSPr2.
Instruction set extensions designed to accelerate multimedia.
Hardware supported virtualization technology.
Each multi-threaded MIPS core can support up to two VPEs (Virtual Processing Elements) which share a single pipeline as well as other hardware resources. However, since each VPE includes a complete copy of the processor state as seen by the software system, each VPE appears as a complete standalone processor to an SMP Linux operating system. For more fine-grained thread processing applications, each VPE is capable of supporting up to nine TCs allocated across two VPEs. The TCs share a common execution unit but each has its own program counter and core register files so that each can handle a thread from the software. The MIPS MT architecture also allows the allocation of processor cycles to threads, and sets the relative thread priorities with an optional Quality of Service (QoS) manager block. This enables two prioritization mechanisms that determine the flow of information across the bus. The first mechanism allows the user to prioritize one thread over another. The second mechanism is used to allocate a specified ratio of the cycles to specific threads over time. The combined use of both mechanisms allows effective allocation of bandwidth to the set of threads, and better control of latencies. In real-time systems, system-level determinism is very critical, and the QoS block facilitates improvement of the predictability of a system. Hardware designers of advanced systems may replace the standard QoS block provided by MIPS Technologies with one that is specifically tuned for their application.
Single-threaded microprocessors today waste many cycles while waiting to access memory, considerably limiting system performance. The use of multi-threading masks the effect of memory latency by increasing processor utilization. As one thread stalls, additional threads are instantly fed into the pipeline and executed, resulting in a significant gain in application throughput. Users can allocate dedicated processing bandwidth to real-time tasks resulting in a guaranteed Quality of Service (QoS). MIPS’ MT technology constantly monitors the progress of threads and dynamically takes corrective actions to meet or exceed the real-time requirements. A processor pipeline can achieve 80-90% utilization by switching threads during data-dependent stalls or cache misses. All of this leads to an improved mobile device user experience, as responsiveness is greatly increased.
SmartMIPS is an Application-Specific Extension (ASE) designed by Gemplus International and MIPS Technologies to improve performance and reduce memory consumption for smart card software. It is supported by MIPS32 only, since smart cards do not require the capabilities of MIPS64 processors. Few smart cards use SmartMIPS.
Open Virtual Platforms (OVP) includes the freely available for non-commercial use simulator OVPsim, a library of models of processors, peripherals and platforms, and APIs which enable users to develop their own models. The models in the library are open source, written in C, and include the MIPS 4K, 24K, 34K, 74K, 1004K, 1074K, M14K, microAptiv, interAptiv, proAptiv 32-bit cores and the MIPS 64-bit 5K range of cores. These models are created and maintained by Imperas and in partnership with MIPS Technologies have been tested and assigned the MIPS-Verified (tm) mark. Sample MIPS-based platforms include both bare metal environments and platforms for booting unmodified Linux binary images. These platforms–emulators are available as source or binaries and are fast, free for non-commercial usage, and are easy to use. OVPsim is developed and maintained by Imperas and is very fast (hundreds of million of instructions per second), and built to handle multicore homogeneous and heterogeneous architectures and systems.
There is a freely available MIPS32 simulator (earlier versions simulated only the R2000/R3000) called SPIM for use in education. EduMIPS64 is a GPL graphical cross-platform MIPS64 CPU simulator, written in Java/Swing. It supports a wide subset of the MIPS64 ISA and allows the user to graphically see what happens in the pipeline when an assembly program is run by the CPU.
MARS is another GUI-based MIPS emulator designed for use in education, specifically for use with Hennessy's Computer Organization and Design.
WebMIPS is a browser-based MIPS simulator with visual representation of a generic, pipelined processor. This simulator is quite useful for register tracking during step by step execution.
More advanced free emulators are available from the GXemul (formerly known as the mips64emul project) and QEMU projects. These emulate the various MIPS III and IV microprocessors in addition to entire computer systems which use them.
Commercial simulators are available especially for the embedded use of MIPS processors, for example Wind River Simics (MIPS 4Kc and 5Kc, PMC RM9000, QED RM7000, Broadcom/Netlogic ec4400, Cavium Octeon I), Imperas (all MIPS32 and MIPS64 cores), VaST Systems (R3000, R4000), and CoWare (the MIPS4KE, MIPS24K, MIPS25Kf and MIPS34K).
WepSIM is a browser-based simulator where a subset of MIPS instructions are micro-programmed. This simulator is very useful in order to learn how a CPU works (microprogramming, MIPS routines, traps, interruptions, system calls, etc.).
The M6100 PICA is a system logic chipset designed by Acer Laboratories introduced in 1993. PICA stands for Performance-enhanced Input-output and CPU Architecture. It was based on the Jazz architecture developed by Microsoft and supported the MIPS Technologies R4000 or R4400 microprocessors. The chipset was designed for computers that run Windows NT, and therefore used ARC firmware to boot Windows NT. The chipset consisted of six chips: a CPU and secondary cache controller, a buffer, a I/O cache and bus controller, a memory controller, and two data buffers.
PICA was used by Acer in its Formula 4000 personal workstation, which NEC sold under the OEM name RISCStation Image.GScube
The GScube was a hardware tool released by Sony intended for use in CGI production houses consisting of a custom variant of sixteen PlayStation 2 motherboards running in parallel. The PlayStation 2 (PS2) is a video game console that was manufactured by Sony Computer Entertainment. It was released on March 4, 2000, in Japan followed by North America and Europe later the same year. It was unveiled that same year at SIGGRAPH; the name "GSCube" is short for Graphics Synthesizer Cube. It was used for two projects, Final Fantasy: The Spirits Within and the film incarnation of Resident Evil.
According to some sources, they were all sent back to Sony in Japan and were subsequently dismantled. They were used for prototyping visual rendering in Final Fantasy, The Matrix and Antz, as well as in a flight simulator. Although the GSCube had good rendering capability, they had a major bottleneck in connecting to external computers to transfer content.Gdium
The Gdium is a subnotebook / netbook computer produced by EMTEC. The Gdium product is distinguished by its unique Loongson MIPS processor and the use of a USB key as a primary storage device. The Gdium netbook is marketed as an interface device to the Gdium "learning community"—a website that provides hardware support, MIPS builds of open-source software, Linux computing tips, and educational resources targeted towards teachers and students within the K-12 demographic.Ingenic Semiconductor
Ingenic Semiconductor is a Chinese fabless semiconductor company based in Beijing, China founded in 2005. They purchased licenses for the MIPS architecture instruction sets in 2009 and design CPU-microarchitectures based on them. They also design system on a chip products including their CPUs and licensed semiconductor intellectual property blocks from third parties, such as Vivante Corporation, commission the fabrication of integrated circuits at semiconductor fabrication plants and sell them.List of MIPS architecture processors
This is a list of processors that implement the MIPS instruction set architecture, sorted by year, process size, frequency, die area, and so on. These processors are designed by Imagination Technologies, MIPS Technologies, and others. It displays an overview of the MIPS processors with performance and functionality versus capabilities for the more recent MIPS Aptiv families.MDMX
The MDMX (MIPS Digital Media eXtension), also known as MaDMaX, is an extension to the MIPS architecture released in October 1996 at the Microprocessor Forum.MIPS-3D
MIPS-3D is an extension to the MIPS V instruction set architecture (ISA) that added 13 new instructions for improving the performance of 3D graphics applications. The instructions improved performance by reducing the number of instructions required to implement four common 3D graphics operations: vertex transformation, clipping, transformation and lighting.
For vertex transformation:
BC1ANY4TFor perspective division and normalization:
MIPS-X is a microprocessor and instruction set architecture developed as a follow-on project to the MIPS project at Stanford University by the same team that developed MIPS. The project, supported by the Defense Advanced Research Projects Agency, started in 1984, and its final form was described in a set of papers released in 1986–87. Unlike its older cousin, MIPS-X was never commercialized as a workstation CPU, and has mainly been seen in embedded designs based on chips designed by Integrated Information Technology for use in digital video applications.
MIPS-X, while designed by the same team and architecturally very similar, is not instruction-set compatible with the mainline MIPS R-series processors. The processor is obscure enough that (as of November 20, 2005) support for it is provided only by specialist developers (such as Green Hills Software), and is notably missing from GCC.
MIPS-X has become important among DVD player firmware hackers, since many DVD players (especially low-end devices) use chips based on the IIT design (and produced by ESS Technology) as their central processor. Devices such as the ESS VideoDrive SoC also include a DSP (co-processor) for decoding MPEG audio and video streams.
The Programmer's Manual describes the hsc instruction [halt and spontaneously combust]. This instruction is executed when a protection violation is detected, but is only present in the -NSA variant of the processor. On other platforms, this type of instruction is known as Halt and Catch Fire.MIPS Technologies
MIPS Technologies, Inc., formerly MIPS Computer Systems, Inc., is an American fabless semiconductor design company that is most widely known for developing the MIPS architecture and a series of RISC CPU chips based on it. MIPS provides processor architectures and cores for digital home, networking, embedded, Internet of things and mobile applications.MIPS Technologies, Inc. is owned by Wave Computing, who acquired it from Tallwood MIPS Inc., a company indirectly owned by Tallwood Venture Capital. Tallwood bought it on 2017-10-25 from Imagination Technologies, a UK-based company best known for their PowerVR graphics processor family. In turn, Imagination Technologies had bought MIPS after CEVA, Inc. pulled out of the bidding on 2013-02-08.MIPS architecture processors
Since 1985, numerous processors implementing some version of the MIPS architecture have been designed and widely used.Namco System 10
The Namco System 10 is an arcade system board released by Namco in 2000 based on the Sony PlayStation hardware. It was preceded by the Namco System 23 in 1997 and succeeded by the Namco System 246.Namco System 11
The Namco System 11 is an arcade system board released by Namco in 1994. The actual hardware is based on Sony's PlayStation home console, and thus many games were ported to that console. The major difference between the two is that the System 11 used surface-mounted ROM chips to store the game data, whereas the PlayStation used CD-ROM. This meant that all System 11 games were unique to the particular system board, and could not be swapped out with another game.
System 11 was succeeded by the System 12 design.Namco System 246
The Namco System 246 is a development of the Sony PlayStation 2 technology as a basis for an arcade system board. It was released in December 2000 on its first game Bloody Roar 3. Like the Sega NAOMI, it is widely licensed for use by other manufacturers. Games such as Battle Gear 3 and Capcom Fighting Evolution are examples of System 246-based arcade games that are not Namco products.Neo Geo X
The Neo Geo X (NGX) is a handheld video game console manufactured by Tommo, licensed by SNK Playmore, and the latest console released as part of the company's Neo Geo brand. Information about the Neo Geo X was first reported in January 2012 and later confirmed in March. It is the first Neo Geo system to be released since the discontinuation of the brand in 2004 and the third Neo Geo handheld device, following the 1999 release of the Neo Geo Pocket Color, which was supported until 2001.
The Neo Geo X features games that were on the popular original Neo Geo (the MVS/AES) hardware, and comes built-in with 20 original Neo Geo games. Additional titles were available on game cards.
The system was released on December 18, 2012 as part of a bundle called the "Neo Geo X Gold Limited Edition", which includes a docking station, an arcade stick, and a bonus game card. The docking station is modeled after the original Neo Geo AES console and is used for charging the handheld as well as connecting it to a television. The arcade stick is a replica of the original Neo Geo AES arcade stick that can be used as a controller when the handheld is connected to a TV through the docking station.NonStop (server computers)
Nonstop is a series of server computers introduced to market in 1976 by Tandem Computers Inc., beginning with the NonStop product line, which was followed by the Hewlett-Packard Integrity NonStop product line extension. Because NonStop systems are based on an integrated hardware/software stack, HP also developed the NonStop OS operating system for them.
NonStop systems are, to an extent, self-healing. To circumvent single points of failure, they are equipped with almost only redundant components. When a mainline component fails, the system automatically falls back to the backup.
These systems are often used by banks, stock exchanges, telecommunication providers and other enterprises requiring extremely high uptime.SGI IRIS 4D
The SGI IRIS 4D series was a line of workstations from Silicon Graphics built in the late-1980s through mid-1990s. They were the first SGI workstations to use the MIPS architecture. The line culminated with the Crimson which was produced until 1997.
== SGI timeline ==SPIM
SPIM is a MIPS processor simulator, designed to run assembly language code for this architecture. The program simulates R2000 and R3000 processors, and was written by James R. Larus while a professor at the University of Wisconsin–Madison. The MIPS machine language is often taught in college-level assembly courses, especially those using the textbook Computer Organization and Design: The Hardware/Software Interface by David A. Patterson and John L. Hennessy (ISBN 1-55860-428-6).
The name of the simulator is a reversal of the letters "MIPS".
SPIM simulators are available for Windows (PCSpim), Mac OS X and Unix/Linux-based (xspim) operating systems. As of release 8.0 in January 2010, the simulator is licensed under the standard BSD license.
In January, 2011, a major release version 9.0 features QtSpim that has a new user interface built on the cross-platform Qt UI framework and runs on Windows, GNU/Linux, and Mac OS X. From this version, the project has also been moved to SourceForge for better maintenance. Precompiled versions of QtSpim for Linux (32-bit), Windows, and Mac OS X, as well as PCSpim for Windows are provided.Sony NEWS
The Sony NEWS ("Network Engineering Workstation", later "NetWorkStation") is a series of Unix workstations sold during the late 1980s and 1990s. The first NEWS machine was the NWS-800, which originally appeared in Japan in January 1987 and was conceived as a desktop replacement for the VAX series of minicomputers.Sun Ray
The Sun Ray from Oracle is a stateless thin client solution aimed at corporate environments, originally introduced by Sun Microsystems in September 1999 and discontinued by Oracle in 2014. It featured a smart card reader and several models featured an integrated flat panel display.
The idea of a stateless desktop was a significant shift from, and the eventual successor to, Sun's earlier line of diskless Java-only desktops, the JavaStation.
Reduced instruction set computer (RISC) architectures