John Leroy Hennessy (born September 22, 1952) is an American computer scientist, academician, businessman, and Chair of Alphabet Inc. Hennessy is one of the founders of MIPS Computer Systems Inc. as well as Atheros and served as the tenth President of Stanford University. Hennessy announced that he would step down in the summer of 2016. He was succeeded as President by Marc Tessier-Lavigne. Marc Andreessen called him "the godfather of Silicon Valley."
Along with David Patterson, Hennessy won the 2017 Turing Award for their work in developing the reduced instruction set computer (RISC) architecture, which is now used in 99% of new computer chips.
|10th President of Stanford University|
|Preceded by||Gerhard Casper|
|Succeeded by||Marc Tessier-Lavigne|
|11th Provost of Stanford University|
|Preceded by||Condoleezza Rice|
|Succeeded by||John Etchemendy|
John Leroy Hennessy
September 22, 1952
Huntington, New York
|Alma mater||Stony Brook University (M.S., 1975; Ph.D., 1977) |
Villanova University (B.S., 1973)
|Known for||RISC, MIPS Technologies, Atheros|
|Awards||Turing Award (2017)|
IEEE Medal of Honor (2012)
Computer History Museum Fellow (2007) 
National Academy of Engineering Member
National Academy of Sciences Member
American Academy of Arts and Sciences Fellow
|Thesis||A real-time language for small processors: design, definition and implementation (1977)|
|Doctoral advisor||Richard Kieburtz|
He earned his bachelor's degree in electrical engineering from Villanova University, and his master's degree and Ph.D. in computer science from Stony Brook University. He is married to his high school sweetheart, Andrea Berti.
Hennessy became a Stanford faculty member in 1977. In 1981, he began the MIPS project to investigate RISC processors, and in 1984, he used his sabbatical year to found MIPS Computer Systems Inc. to commercialize the technology developed by his research. In 1987, he became the Willard and Inez Kerr Bell Endowed Professor of Electrical Engineering and Computer Science.
Hennessy served as director of Stanford's Computer System Laboratory (1989–93), a research center run by Stanford's Electrical Engineering and Computer Science departments. He was chair of the Department of Computer Science (1994–96) and Dean of the School of Engineering (1996–99).
In 1999, Stanford President Gerhard Casper appointed Hennessy to succeed Condoleezza Rice as Provost of Stanford University. When Casper stepped down to focus on teaching in 2000, the Stanford Board of Trustees named Hennessy to succeed Casper as president. In 2008, Hennessy earned a salary of $1,091,589 ($702,771 base salary, $259,592 deferred benefits, $129,226 non-tax benefits), the 23rd highest among all American university presidents.
In 2007, he was made a Fellow of the Computer History Museum "for fundamental contributions to engineering education, advances in computer architecture, and the integration of leading-edge research with education".
In December 2010, Hennessy coauthored an editorial with Harvard University President Drew Gilpin Faust urging the passage of the DREAM Act; the legislation did not pass the 111th United States Congress.
In 2012, Hennessy was awarded the IEEE Medal of Honor. The IEEE awarded Hennessy their highest recognition "for pioneering the RISC processor architecture and for leadership in computer engineering and higher education". In 2012, Hennessy received an honorary doctor of mathematics degree from the University of Waterloo (Canada), in celebration of his profound contributions to modern computer architecture and to post-secondary education.
In 2013, Hennessy became a judge for the inaugural Queen Elizabeth Prize for Engineering. He has remained on the judging panel for the subsequent awards in 2015 and 2017.
In June 2015, Hennessy announced that he would step down as Stanford president in summer 2016.
In 2016, Hennessy co-founded the Knight-Hennessy Scholars program; he serves as its inaugural director. The program has a $750 million endowment to fully fund graduate students at Stanford for up to three years. The inaugural class of 51 scholars from 21 countries will arrive at Stanford in the fall of 2018.
On March 21, 2018, together with David Patterson, he was awarded the 2017 ACM A.M. Turing Award for the development of the reduced instruction set computer (RISC) architecture in the 1980s.. The award praised them for "pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry".
Hennessy has a history of strong interest and involvement in college-level computer education. He co-authored, with David A. Patterson, two well-known books on computer architecture, Computer Organization and Design: the Hardware/Software Interface and Computer Architecture: A Quantitative Approach, which introduced the DLX RISC architecture. They have been widely used as textbooks for graduate and undergraduate courses since 1990.
Hennessy also contributed to updating Donald Knuth's MIX processor to the MMIX. Both are model computers used in Knuth's classic series, The Art of Computer Programming. MMIX is Knuth's DLX equivalent.
In 2004, he was awarded the Association for Computing Machinery SIGARCH ISCA Influential Paper Award for his 1989 co-authored paper on high performing cache hierarchies. He received the award again in 2009 for his 1994 co-authored paper on the Stanford FLASH multiprocessor.
| Provost of Stanford University
| President of Stanford University
BigQuery is a RESTful web service that enables interactive analysis of massively large datasets working in conjunction with Google Storage. It is a serverless Platform as a Service (PaaS) that may be used complementarily with MapReduce.Computer architecture
In computer engineering, computer architecture is a set of rules and methods that describe the functionality, organization, and implementation of computer systems. Some definitions of architecture define it as describing the capabilities and programming model of a computer but not a particular implementation. In other definitions computer architecture involves instruction set architecture design, microarchitecture design, logic design, and implementation.DLX
The DLX (pronounced "Deluxe") is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the Stanford MIPS and the Berkeley RISC designs (respectively), the two benchmark examples of RISC design (named after the Berkeley design).
The DLX is essentially a cleaned up (and modernized) simplified MIPS CPU. The DLX has a simple 32-bit load/store architecture, somewhat unlike the modern MIPS CPU. As the DLX was intended primarily for teaching purposes, the DLX design is widely used in university-level computer architecture courses.
There are two known implementations: ASPIDA and VAMP. ASPIDA project resulted in a core with many nice features: open source, supports Wishbone, asynchronous design, supports multiple ISA's, ASIC proven. VAMP is a DLX-variant that was mathematically verified as part of Verisoft project. It was specified with PVS, implemented in Verilog, and runs on a Xilinx FPGA. A full stack from compiler to kernel to TCP/IP was built on it.Daniel Pearl Foundation
The Daniel Pearl Foundation is a foundation based in the United States. The foundation was formed by his parents Ruth and Judea Pearl after musician and Wall Street Journal reporter Daniel Pearl was kidnapped and murdered by terrorists in 2002. The organization's mission is to promote cross-cultural understanding through journalism, music, and innovative communications.
The honorary board of the Daniel Pearl Foundation includes Christiane Amanpour; former President Bill Clinton; Abdul Sattar Edhi; Danny Gill; John L. Hennessy; Ted Koppel; Queen Noor of Jordan; Sari Nusseibeh; Mariane Pearl; Itzhak Perlman; Harold M. Schulweis; Craig Sherman; Paul Steiger; and Elie Wiesel.David Patterson (computer scientist)
David Andrew Patterson (born November 16, 1947) is an American computer pioneer and academic who has held the position of Professor of Computer Science at the University of California, Berkeley since 1976. He announced retirement in 2016 after serving nearly forty years, becoming a distinguished engineer at Google. He currently is Vice Chair of the Board of Directors of the RISC-V Foundation, and the Pardee Professor of Computer Science, Emeritus at UC Berkeley.
Patterson is noted for his pioneering contributions to RISC processor design, having coined the term RISC, and by leading the Berkeley RISC project.As of 2018, 99% of all new chips use the RISC architecture. He is also noted for leading the research on RAID storage together with Randy Katz.His books on computer architecture (co-authored with John L. Hennessy) are widely used in computer science education. Along with Hennessy, Patterson won the 2017 Turing Award for their work in developing RISC.Federated Computing Research Conference
The Federated Computing Research Conference, FCRC, is an event that brings together several academic conferences, workshops, and plenary talks in the field of computer science. FCRC has been organised in 1993, 1996, 1999, 2003, 2007, 2011 and 2015. The 2019 event will be held in Phoenix, Arizona.
In the first FCRC, the main organiser was the Computing Research Association; since then, the Association for Computing Machinery has taken the lead in organising the event.
The Turing Award 1998, 2002, 2006, and 2010 recipients gave plenary talks in FCRC 1999, 2003, 2007, and 2011. Other plenary speakers in FCRC include László Babai, Charles Bennett, Randal Bryant, Bob Colwell, David Culler, Cynthia Dwork, Shafi Goldwasser, Michael J. Flynn, Hector Garcia-Molina, John L. Hennessy, Richard Karp, Randy Katz, Ken Kennedy, James Kurose, Ed Lazowska, Barbara Liskov, Robin Milner, Charles R. (Chuck) Moore, Christos Papadimitriou, Michael Rabin, Scott Shenker, Burton Smith, Guy L. Steele, Jr., Avi Wigderson, Maurice Wilkes, William A. Wulf.Google Dataset Search
Google Dataset Search is a search engine from Google that helps researchers locate online data that is freely available for use. The company launched the service on September 5, 2018, and stated that the product was targeted at scientists and data journalists.
Google Dataset Search complements Google Scholar, the company's search engine for academic studies and reports.Google Finance
Google Finance is a website focusing on business news and financial information hosted by Google.Google Fit
Google Fit is a health-tracking platform developed by Google for the Android operating system and Wear OS. It is a single set of APIs that blends data from multiple apps and devices. Google Fit uses sensors in a user's activity tracker or mobile device to record physical fitness activities (such as walking or cycling), which are measured against the user's fitness goals to provide a comprehensive view of their fitness.Google Forms
Google Forms is a survey administration app that is included in the Google Drive office suite along with Google Docs, Google Sheets, and Google Slides.
Forms features all of the collaboration and sharing features found in Docs, Sheets, and Slides.Instruction unit
The instruction unit (IU) in a central processing unit (CPU) is responsible for organising program instructions to be fetched from memory, and executed, in an appropriate order. It is a part of the control unit, which in turn is part of the CPU.
In the simplest style of computer architecture, the instruction cycle is very rigid, and runs exactly as specified by the programmer.
In the Instruction Fetch part of the cycle,
the contents of the program counter (PC) register are placed on the address bus, and sent to the memory unit;
the memory unit returns the instruction at that address, and it is latched into the Instruction Register (IR);
and the contents of the PC are incremented or over-written by a new value (in the case of a Jump or Branch instruction) ready for the next instruction cycle.
This becomes a lot more complicated, though, once performance-enhancing features are added, such as instruction pipelining, out-of-order execution, and even just the introduction of a simple instruction cache.International Symposium on Computer Architecture
The International Symposium on Computer Architecture (ISCA) is an annual academic conference on computer architecture, generally viewed as the top-tier in the field. Association for Computing Machinery's Special Interest Group on Computer Architecture (ACM SIGARCH) and Institute of Electrical and Electronics Engineers Computer Society are technical sponsors.
ISCA has participated in the Federated Computing Research Conference in 1993, 1996, 1999, 2003, 2007, 2011 and 2015, every year that the conference has been organized.John Etchemendy
John W. Etchemendy (born 1952 in Reno, Nevada) was Stanford University's twelfth Provost. He succeeded John L. Hennessy to the post on September 1, 2000 and stepped down on January 31, 2017.Load–store unit
In computer engineering a load–store unit is a specialized execution unit responsible for executing all load and store instructions, generating virtual addresses of load and store operations and loading data from memory or storing it back to memory from registers.The load–store unit usually includes a queue which acts as a waiting area for memory instructions, and the unit itself operates independently of other processor units.Load–store units may also be used in vector processing, and in such cases the term "load–store vector" may be used.Some load-store units are also capable of executing simple fixed-point and/or integer operations.MMIX
MMIX (pronounced em-mix) is a 64-bit reduced instruction set computing (RISC) architecture designed by Donald Knuth, with significant contributions by John L. Hennessy (who contributed to the design of the MIPS architecture) and Richard L. Sites (who was an architect of the Alpha architecture). Knuth has said that "MMIX is a computer intended to illustrate machine-level aspects of programming. In my books The Art of Computer Programming, it replaces MIX, the 1960s-style machine that formerly played such a role… I strove to design MMIX so that its machine language would be simple, elegant, and easy to learn. At the same time I was careful to include all of the complexities needed to achieve high performance in practice, so that MMIX could in principle be built and even perhaps be competitive with some of the fastest general-purpose computers in the marketplace."Marc Tessier-Lavigne
Marc Trevor Tessier-Lavigne (born December 18, 1959) is a Canadian neuroscientist who is the 11th and current president of Stanford University. Previously, he was a professor at the University of California, San Francisco and then president of Rockefeller University in New York City. He was formerly executive vice president for research and the Chief Scientific Officer at Genentech. He was the first industry executive to assume the Rockefeller presidency. He is also a member of the Cure Alzheimer's Fund's Scientific Advisory Board.SPIM
SPIM is a MIPS processor simulator, designed to run assembly language code for this architecture. The program simulates R2000 and R3000 processors, and was written by James R. Larus while a professor at the University of Wisconsin–Madison. The MIPS machine language is often taught in college-level assembly courses, especially those using the textbook Computer Organization and Design: The Hardware/Software Interface by David A. Patterson and John L. Hennessy (ISBN 1-55860-428-6).
The name of the simulator is a reversal of the letters "MIPS".
SPIM simulators are available for Windows (PCSpim), Mac OS X and Unix/Linux-based (xspim) operating systems. As of release 8.0 in January 2010, the simulator is licensed under the standard BSD license.
In January, 2011, a major release version 9.0 features QtSpim that has a new user interface built on the cross-platform Qt UI framework and runs on Windows, GNU/Linux, and Mac OS X. From this version, the project has also been moved to SourceForge for better maintenance. Precompiled versions of QtSpim for Linux (32-bit), Windows, and Mac OS X, as well as PCSpim for Windows are provided.Stanford DASH
Stanford DASH was a cache coherent multiprocessor developed in the late 1980s by a group led by Anoop Gupta, John L. Hennessy, Mark Horowitz, and Monica S. Lam at Stanford University. It was based on adding a pair of directory boards designed at Stanford to up to 16 SGI IRIS 4D Power Series machines and then cabling the systems in a mesh topology using a Stanford-modified version of the Torus Routing Chip. The boards designed at Stanford implemented a directory-based cache coherence protocol allowing Stanford DASH to support distributed shared memory for up to 64 processors. Stanford DASH was also notable for both supporting and helping to formalize weak memory consistency models, including release consistency. Because Stanford DASH was the first operational machine to include scalable cache coherence, it influenced subsequent computer science research as well as the commercially available SGI Origin 2000. Stanford DASH is included in the 25th anniversary retrospective of selected papers from the International Symposium on Computer Architecture and several computer science books, has been simulated by the University of Edinburgh, and is used as a case study in contemporary computer science classes.Stanford MIPS
MIPS (an acronym for Microprocessor without Interlocked Pipeline Stages) was a research project conducted by John L. Hennessy at Stanford University between 1981 and 1984. MIPS investigated a type of instruction set architecture (ISA) now called Reduced Instruction Set Computer (RISC), its implementation as a microprocessor with very large scale integration (VLSI) semiconductor technology, and the effective exploitation of RISC architectures with optimizing compilers. MIPS, together with the IBM 801 and Berkeley RISC, were the three research projects that pioneered and popularized RISC technology in the mid-1980s. In recognition of the impact MIPS made on computing, Hennessey was awarded the IEEE John von Neumann Medal in 2000 by the IEEE (shared with David A. Patterson), the Eckert–Mauchly Award in 2001 by the Association for Computing Machinery, the Seymour Cray Computer Engineering Award in 2001 by the IEEE Computer Society, and, again with David Patterson, the Turing Award in 2017 by the ACM.
The project was initiated in 1981 in response to reports of similar projects at IBM (the 801) and the University of California, Berkeley (the RISC). MIPS was conducted by Hennessy and his graduate students until its conclusion in 1984. Hennessey founded MIPS Computer Systems in the same year to commercialize the technology developed by the project. In 1985, MIPS Computer Systems announced a new ISA, also called MIPS, and its first implementation, the R2000 microprocessor. The commercial MIPS ISA, and its implementations went on to be widely used, appearing in embedded computers, personal computers, workstations, servers, and supercomputers. As of May 2017, the commercial MIPS ISA is owned by Imagination Technologies, and is used mainly in embedded computers. In the late 1980s, a follow-up project called MIPS-X was conducted by Hennessy at Stanford.
The MIPS ISA was based on a 32-bit word. It supported 32-bit addressing, and was word-addressed. It was a load/store architecture—all references to memory used load and store instructions that copied data between the main memory and 32 general-purpose registers (GPRs). All other instructions, such as integer arithmetic, operated on the GPRs. It possessed a basic instruction set consisting of instructions for control flow, integer arithmetic, and logical operations. To minimize pipeline stalls, all instructions except for load and store had to be executed in one clock cycle. There were no instructions for integer multiplication or division, or operations for floating-point numbers. The architecture exposed all hazards caused by the five-stage pipeline with delay slots. The compiler scheduled instructions to avoid hazards resulting in incorrect computation whilst simultaneously ensuring that the generated code minimized execution time. MIPS instructions are 16 or 32 bit long. The decision to expose all hazards was motivated by the desire to maximize performance by minimizing critical paths, which interlock circuits lengthened. Instructions were packed into 32-bit instruction words (as MIPS is word-addressed). A 32-bit instruction word could contain two 16-bit operations. These were included to reduce the size of machine code. The MIPS microprocessor was implemented in NMOS logic.
Stanford University presidents
Stanford University provosts
A. M. Turing Award laureates