High-κ dielectric

The term high-κ dielectric refers to a material with a high dielectric constant κ (as compared to silicon dioxide). High-κ dielectrics are used in semiconductor manufacturing processes where they are usually used to replace a silicon dioxide gate dielectric or another dielectric layer of a device. The implementation of high-κ gate dielectrics is one of several strategies developed to allow further miniaturization of microelectronic components, colloquially referred to as extending Moore's Law.

Sometimes these materials are called "high-k" instead of "high-κ" (high kappa).

Need for high-κ materials

Silicon dioxide (SiO2) has been used as a gate oxide material for decades. As transistors have decreased in size, the thickness of the silicon dioxide gate dielectric has steadily decreased to increase the gate capacitance and thereby drive current, raising device performance. As the thickness scales below 2 nm, leakage currents due to tunneling increase drastically, leading to high power consumption and reduced device reliability. Replacing the silicon dioxide gate dielectric with a high-κ material allows increased gate capacitance without the associated leakage effects.

First principles

The gate oxide in a MOSFET can be modeled as a parallel plate capacitor. Ignoring quantum mechanical and depletion effects from the Si substrate and gate, the capacitance C of this parallel plate capacitor is given by

Conventional silicon dioxide gate dielectric structure compared to a potential high-k dielectric structure where κ = 16
FET cross section
Cross-section of an n-channel MOSFET transistor showing the gate oxide dielectric


Since leakage limitation constrains further reduction of t, an alternative method to increase gate capacitance is alter κ by replacing silicon dioxide with a high-κ material. In such a scenario, a thicker gate oxide layer might be used which can reduce the leakage current flowing through the structure as well as improving the gate dielectric reliability.

Gate capacitance impact on drive current

The drain current ID for a MOSFET can be written (using the gradual channel approximation) as


  • W is the width of the transistor channel
  • L is the channel length
  • μ is the channel carrier mobility (assumed constant here)
  • Cinv is the capacitance density associated with the gate dielectric when the underlying channel is in the inverted state
  • VG is the voltage applied to the transistor gate
  • Vth is the threshold voltage

The term VG − Vth is limited in range due to reliability and room temperature operation constraints, since a too large VG would create an undesirable, high electric field across the oxide. Furthermore, Vth cannot easily be reduced below about 200 mV, because leakage currents due to increased oxide leakage (that is, assuming high-κ dielectrics are not available) and subthreshold conduction raise stand-by power consumption to unacceptable levels. (See the industry roadmap,[1] which limits threshold to 200 mV, and Roy et al. [2]). Thus, according to this simplified list of factors, an increased ID,sat requires a reduction in the channel length or an increase in the gate dielectric capacitance.

Materials and considerations

Replacing the silicon dioxide gate dielectric with another material adds complexity to the manufacturing process. Silicon dioxide can be formed by oxidizing the underlying silicon, ensuring a uniform, conformal oxide and high interface quality. As a consequence, development efforts have focused on finding a material with a requisitely high dielectric constant that can be easily integrated into a manufacturing process. Other key considerations include band alignment to silicon (which may alter leakage current), film morphology, thermal stability, maintenance of a high mobility of charge carriers in the channel and minimization of electrical defects in the film/interface. Materials which have received considerable attention are hafnium silicate, zirconium silicate, hafnium dioxide and zirconium dioxide, typically deposited using atomic layer deposition.

It is expected that defect states in the high-k dielectric can influence its electrical properties. Defect states can be measured for example by using zero-bias thermally stimulated current, zero-temperature-gradient zero-bias thermally stimulated current spectroscopy,[3][4] or inelastic electron tunneling spectroscopy (IETS).

Use in industry

The industry has employed oxynitride gate dielectrics since the 1990s, wherein a conventionally formed silicon oxide dielectric is infused with a small amount of nitrogen. The nitride content subtly raises the dielectric constant and is thought to offer other advantages, such as resistance against dopant diffusion through the gate dielectric.

In early 2007, Intel announced the deployment of hafnium-based high-k dielectrics in conjunction with a metallic gate for components built on 45 nanometer technologies, and has shipped it in the 2007 processor series codenamed Penryn.[5][6] At the same time, IBM announced plans to transition to high-k materials, also hafnium-based, for some products in 2008. While not identified, the most likely dielectric used in such applications are some form of nitrided hafnium silicates (HfSiON). HfO2 and HfSiO are susceptible to crystallization during dopant activation annealing. NEC Electronics has also announced the use of a HfSiON dielectric in their 55 nm UltimateLowPower technology.[7] However, even HfSiON is susceptible to trap-related leakage currents, which tend to increase with stress over device lifetime. This leakage effect becomes more severe as hafnium concentration increases. There is no guarantee however, that hafnium will serve as a de facto basis for future high-k dielectrics. The 2006 ITRS roadmap predicted the implementation of high-k materials to be commonplace in the industry by 2010.

See also


  1. ^ "Process Integration, Devices, and Structures" (PDF). International Technology Roadmap for Semiconductors: 2006 Update. Archived from the original (PDF) on 2007-09-27.
  2. ^ Kaushik Roy, Kiat Seng Yeo (2004). Low Voltage, Low Power VLSI Subsystems. McGraw-Hill Professional. Fig. 2.1, p. 44. ISBN 978-0-07-143786-8.
  3. ^ Lau, W. S.; Zhong, L.; Lee, Allen; See, C. H.; Han, Taejoon; Sandler, N. P.; Chong, T. C. (1997). "Detection of defect states responsible for leakage current in ultrathin tantalum pentoxide (Ta[sub 2]O[sub 5]) films by zero-bias thermally stimulated current spectroscopy". Applied Physics Letters. 71 (4): 500. Bibcode:1997ApPhL..71..500L. doi:10.1063/1.119590.
  4. ^ Lau, W. S.; Wong, K. F.; Han, Taejoon; Sandler, Nathan P. (2006). "Application of zero-temperature-gradient zero-bias thermally stimulated current spectroscopy to ultrathin high-dielectric-constant insulator film characterization". Applied Physics Letters. 88 (17): 172906. Bibcode:2006ApPhL..88q2906L. doi:10.1063/1.2199590.
  5. ^ "Intel 45nm High-k Silicon Technology Page". Intel.com. Retrieved 2011-11-08.
  6. ^ IEEE Spectrum: The High-k Solution
  7. ^ "UltimateLowPower Technology|Advanced Process Technology|Technology|NEC Electronics". Necel.com. Archived from the original on 2010-02-19. Retrieved 2011-11-08.

Further reading

45 nanometer

Per the International Technology Roadmap for Semiconductors, the 45 nanometer (45 nm) technology node should refer to the average half-pitch of a memory cell manufactured at around the 2007–2008 time frame.

Matsushita and Intel started mass-producing 45 nm chips in late 2007, and AMD started production of 45 nm chips in late 2008, while IBM, Infineon, Samsung, and Chartered Semiconductor have already completed a common 45 nm process platform. At the end of 2008, SMIC was the first China-based semiconductor company to move to 45 nm, having licensed the bulk 45 nm process from IBM.

Many critical feature sizes are smaller than the wavelength of light used for lithography (i.e., 193 nm and 248 nm). A variety of techniques, such as larger lenses, are used to make sub-wavelength features. Double patterning has also been introduced to assist in shrinking distances between features, especially if dry lithography is used. It is expected that more layers will be patterned with 193 nm wavelength at the 45 nm node. Moving previously loose layers (such as Metal 4 and Metal 5) from 248 nm to 193 nm wavelength is expected to continue, which will likely further drive costs upward, due to difficulties with 193 nm photoresists.

Antenna effect

The antenna effect, more formally plasma induced gate oxide damage, is an effect that can potentially cause yield and reliability problems during the manufacture of MOS integrated circuits. Fabs normally supply antenna rules, which are rules that must be obeyed to avoid this problem. A violation of such rules is called an antenna violation. The word antenna is something of a misnomer in this context—the problem is really the collection of charge, not the normal meaning of antenna, which is a device for converting electromagnetic fields to/from electrical currents. Occasionally the phrase antenna effect is used in this context, but this is less common since there are many effects, and the phrase does not make clear which is meant.

Figure 1(a) shows a side view of a typical net in an integrated circuit. Each net will include at least one driver, which must contain a source or drain diffusion (in newer technology implantation is used), and at least one receiver, which will consist of a gate electrode over a thin gate dielectric (see Figure 2 for a detailed view of a MOS transistor). Since the gate dielectric is so thin, only a few molecules thick, a big worry is breakdown of this layer. This can happen if the net somehow acquires a voltage somewhat higher than the normal operating voltage of the chip. (Historically, the gate dielectric has been silicon dioxide, so most of the literature refers to gate oxide damage or gate oxide breakdown. As of 2007, some manufacturers are replacing this oxide with various high-κ dielectric materials which may or may not be oxides, but the effect is still the same.)

Once the chip is fabricated, this cannot happen, since every net has at least some source/drain implant connected to it. The source/drain implant forms a diode, which breaks down at a lower voltage than the oxide (either forward diode conduction, or reverse breakdown), and does so non-destructively. This protects the gate oxide.

However, during the construction of the chip, the oxide may not be protected by a diode. This is shown in figure 1(b), which is the situation while metal 1 is being etched. Since metal 2 is not built yet, there is no diode connected to the gate oxide. So if a charge is added in any way to the metal 1 shape (as shown by the lightning bolt) it can rise to the level of breaking down the gate oxide. In particular, reactive-ion etching of the first metal layer can result in exactly the situation shown - the metal on each net is disconnected from the initial global metal layer, and the plasma etching is still adding charges to each piece of metal.

Leaky gate oxides, although bad for power dissipation, are good for avoiding damage from the antenna effect. A leaky oxide can prevent a charge from building up to the point of causing oxide breakdown. This leads to the somewhat surprising observation that a very thin gate oxide is less likely to be damaged than a thick gate oxide, because as the oxide grows thinner, the leakage goes up exponentially, but the breakdown voltage shrinks only linearly.

Atomic layer etching

Atomic layer etching is an emerging technique in semiconductor manufacture, in which a sequence alternating between self-limiting chemical modification steps which affect only the top atomic layers of the wafer, and etching steps which remove only the chemically-modified areas, allows the removal of individual atomic layers. The standard example is etching of silicon by alternating reaction with chlorine and etching with argon ions.

This is a better-controlled process than reactive ion etching, though the issue with commercial use of it has been throughput; sophisticated gas handling is required, and removal rates of one atomic layer per second are around the state of the art.The equivalent process for depositing material is atomic layer deposition (ALD). ALD is substantially more mature, having been used by Intel for high-κ dielectric layers since 2007 and in Finland in the fabrication of thin film electroluminescent devices since 1985.


Complementary metal–oxide–semiconductor (CMOS) is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors (CMOS sensor), data converters, and highly integrated transceivers for many types of communication. Frank Wanlass patented CMOS in 1963 (US patent 3,356,858) while working for Fairchild Semiconductor.

CMOS is also sometimes referred to as complementary-symmetry metal–oxide–semiconductor (COS-MOS).

The words "complementary-symmetry" refer to the typical design style with CMOS using complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions.Two important characteristics of CMOS devices are high noise immunity and low static power consumption.

Since one transistor of the pair is always off, the series combination draws significant power only momentarily during switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor–transistor logic (TTL) or N-type metal-oxide-semiconductor logic (NMOS) logic, which normally have some standing current even when not changing state. CMOS also allows a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most used technology to be implemented in very-large-scale integration (VLSI) chips.

The phrase "metal–oxide–semiconductor" is a reference to the physical structure of certain field-effect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor material. Aluminium was once used but now the material is polysilicon. Other metal gates have made a comeback with the advent of high-κ dielectric materials in the CMOS process, as announced by IBM and Intel for the 45 nanometer node and smaller sizes.

Hafnium dioxide

Hafnium(IV) oxide is the inorganic compound with the formula HfO2. Also known as hafnia, this colourless solid is one of the most common and stable compounds of hafnium. It is an electrical insulator with a band gap of 5.3~5.7 eV. Hafnium dioxide is an intermediate in some processes that give hafnium metal.

Hafnium(IV) oxide is quite inert. It reacts with strong acids such as concentrated sulfuric acid and with strong bases. It dissolves slowly in hydrofluoric acid to give fluorohafnate anions. At elevated temperatures, it reacts with chlorine in the presence of graphite or carbon tetrachloride to give hafnium tetrachloride.

Lau Wai Shing

Lau Wai Shing (Chinese: 劉偉成; born 29 July 1955 in Hong Kong), also known as Wai Shing Lau, is a Hong Kong electrical engineer and materials scientist. He worked on both Si-based and III-V based microelectronics.

Low-κ dielectric

In semiconductor manufacturing, a low-κ is a material with a small relative dielectric constant relative to silicon dioxide. Although the proper symbol for the relative dielectric constant is the Greek letter κ (kappa), in conversation such materials are referred to as being "low-k" (low-kay) rather than "low-κ" (low-kappa). Low-κ dielectric material implementation is one of several strategies used to allow continued scaling of microelectronic devices, colloquially referred to as extending Moore's law. In digital circuits, insulating dielectrics separate the conducting parts (wire interconnects and transistors) from one another. As components have scaled and transistors have gotten closer together, the insulating dielectrics have thinned to the point where charge build up and crosstalk adversely affect the performance of the device. Replacing the silicon dioxide with a low-κ dielectric of the same thickness reduces parasitic capacitance, enabling faster switching speeds and lower heat dissipation.


The metal-oxide-semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is a type of field-effect transistor (FET), most commonly fabricated by the controlled oxidation of silicon. It has an insulated gate, whose voltage determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. A metal-insulator-semiconductor field-effect transistor or MISFET is a term almost synonymous with MOSFET. Another synonym is IGFET for insulated-gate field-effect transistor.

The basic principle of the field-effect transistor was first patented by Julius Edgar Lilienfeld in 1925.The main advantage of a MOSFET is that it requires almost no input current to control the load current, when compared with bipolar transistors. In an enhancement mode MOSFET, voltage applied to the gate terminal increases the conductivity of the device. In depletion mode transistors, voltage applied at the gate reduces the conductivity.The "metal" in the name MOSFET is sometimes a misnomer, because the gate material can be a layer of polysilicon (polycrystalline silicon). Similarly, "oxide" in the name can also be a misnomer, as different dielectric materials are used with the aim of obtaining strong channels with smaller applied voltages.

The MOSFET is by far the most common transistor in digital circuits, as billions may be included in a memory chip or microprocessor. Since MOSFETs can be made with either p-type or n-type semiconductors, complementary pairs of MOS transistors can be used to make switching circuits with very low power consumption, in the form of CMOS logic.

Multigate device

A multigate device or multiple-gate field-effect transistor (MuGFET) refers to a MOSFET (metal–oxide–semiconductor field-effect transistor) that incorporates more than one gate into a single device. The multiple gates may be controlled by a single gate electrode, wherein the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes. A multigate device employing independent gate electrodes is sometimes called a multiple-independent-gate field-effect transistor (MIGFET).

Multigate transistors are one of the several strategies being developed by CMOS semiconductor manufacturers to create ever-smaller microprocessors and memory cells, colloquially referred to as extending Moore's law.Development efforts into multigate transistors have been reported by AMD, Hitachi, IBM, Infineon Technologies, Intel Corporation, TSMC, Freescale Semiconductor, University of California, Berkeley, and others, and the ITRS predicted correctly that such devices will be the cornerstone of sub-32 nm technologies. The primary roadblock to widespread implementation is manufacturability, as both planar and non-planar designs present significant challenges, especially with respect to lithography and patterning. Other complementary strategies for device scaling include channel strain engineering, silicon-on-insulator-based technologies, and high-κ/metal gate materials.

Dual-gate MOSFETs are commonly used in very high frequency (VHF) mixers and in sensitive VHF front-end amplifiers. They are available from manufacturers such as Motorola, NXP Semiconductors, and Hitachi.

Thin-film transistor

A thin-film transistor (TFT) is a special kind of field-effect transistor made by depositing thin films of an active semiconductor layer as well as the dielectric layer and metallic contacts over a supporting (but non-conducting) substrate. A common substrate is glass, because the primary application of TFTs is in liquid-crystal displays (LCDs). This differs from the conventional transistor, where the semiconductor material typically is the substrate, such as a silicon wafer.

Woodward effect

The Woodward effect, also referred to as a Mach effect, is part of a hypothesis proposed by James F. Woodward in 1990. The hypothesis states that transient mass fluctuations arise in any object that absorbs internal energy while undergoing a proper acceleration. Harnessing this effect could generate a reactionless thrust, which Woodward and others claim to measure in various experiments.Hypothetically, the Woodward effect would allow for field propulsion spacecraft engines that would not have to expel matter. Such a proposed engine, is sometimes called a Mach effect thruster (MET) or a Mach Effect Gravitational Assist (MEGA) drive. So far, experimental results have not strongly supported this hypothesis, but experimental research on this effect, and its potential applications, continues. The anomalous thrust detected in some RF resonant cavity thruster (EmDrive/Cannae drive) experiments may be explained by the same type of Mach effect proposed by Woodward, however it has since been challenged and an explanation was proposed as interactions between its electric cables and the earth's magnetic field. The Space Studies Institute was selected as part of NASA's Innovative Advanced Concepts program as a Phase I proposal in April 2017 for Mach Effect research. The year after, NASA awarded a NIAC Phase II grant to the SSI to further develop these propellantless thrusters.The effect is controversial within mainstream physics because the underlying model proposed for it appears to be faulty, resulting in violations of energy conservation as well as momentum conservation. Due to these flaws, some scientists argue that the effect cannot exist; alternatively, if a real effect is measured, then the model that is the reason for proposing that the effect exists cannot be an accurate description of the measured effect.

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