Field-programmable gate array

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence the term "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). Circuit diagrams were previously used to specify the configuration, but this is increasingly rare due to the advent of electronic design automation tools.

Fpga xilinx spartan
A Spartan FPGA from Xilinx

FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together", like many logic gates that can be inter-wired in different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.[1] Many FPGAs can be reprogrammed to implement different logic functions,[2] allowing flexible reconfigurable computing as performed in computer software.

Altera StratixIVGX FPGA
A Stratix IV FPGA from Altera

Technical design

Contemporary field-programmable gate arrays (FPGAs) have large resources of logic gates and RAM blocks to implement complex digital computations.[2] As FPGA designs employ very fast I/O rates and bidirectional data buses, it becomes a challenge to verify correct timing of valid data within setup time and hold time.

Floor planning enables resource allocation within FPGAs to meet these time constraints. FPGAs can be used to implement any logical function that an ASIC can perform. The ability to update the functionality after shipping, partial re-configuration of a portion of the design[3] and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.[1]

Some FPGAs have analog features in addition to digital functions. The most common analog feature is a programmable slew rate on each output pin, allowing the engineer to set low rates on lightly loaded pins that would otherwise ring or couple unacceptably, and to set higher rates on heavily loaded pins on high-speed channels that would otherwise run too slowly.[4][5] Also common are quartz-crystal oscillators, on-chip resistance-capacitance oscillators, and phase-locked loops with embedded voltage-controlled oscillators used for clock generation and management and for high-speed serializer-deserializer (SERDES) transmit clocks and receiver clock recovery. Fairly common are differential comparators on input pins designed to be connected to differential signaling channels. A few "mixed signal FPGAs" have integrated peripheral analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) with analog signal conditioning blocks allowing them to operate as a system-on-a-chip (SoC).[6] Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, and field-programmable analog array (FPAA), which carries analog values on its internal programmable interconnect fabric.

History

The FPGA industry sprouted from programmable read-only memory (PROM) and programmable logic devices (PLDs). PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field-programmable). However, programmable logic was hard-wired between logic gates.[7]

Altera was founded in 1983 and delivered the industry's first reprogrammable logic device in 1984 – the EP300 – which featured a quartz window in the package that allowed users to shine an ultra-violet lamp on the die to erase the EPROM cells that held the device configuration.[8] In December 2015, Intel acquired Altera.

Xilinx co-founders Ross Freeman and Bernard Vonderschmitt invented the first commercially viable field-programmable gate array in 1985 – the XC2064.[9] The XC2064 had programmable gates and programmable interconnects between gates, the beginnings of a new technology and market.[10] The XC2064 had 64 configurable logic blocks (CLBs), with two three-input lookup tables (LUTs).[11] More than 20 years later, Freeman was entered into the National Inventors Hall of Fame for his invention.[12][13]

In 1987, the Naval Surface Warfare Center funded an experiment proposed by Steve Casselman to develop a computer that would implement 600,000 reprogrammable gates. Casselman was successful and a patent related to the system was issued in 1992.[7]

Altera and Xilinx continued unchallenged and quickly grew from 1985 to the mid-1990s, when competitors sprouted up, eroding significant market share. By 1993, Actel (now Microsemi) was serving about 18 percent of the market.[10] By 2013, Altera (31 percent), Actel (10 percent) and Xilinx (36 percent) together represented approximately 77 percent of the FPGA market.[14]

The 1990s were a period of rapid growth for FPGAs, both in circuit sophistication and the volume of production. In the early 1990s, FPGAs were primarily used in telecommunications and networking. By the end of the decade, FPGAs found their way into consumer, automotive, and industrial applications.[15]

21st century developments

A recent trend has been to take the coarse-grained architectural approach a step further by combining the logic blocks and interconnects of traditional FPGAs with embedded microprocessors and related peripherals to form a complete "system on a programmable chip". This work mirrors the architecture created by Ron Perlof and Hana Potash of Burroughs Advanced Systems Group in 1982 which combined a reconfigurable CPU architecture on a single chip called the SB24.

Examples of such hybrid technologies can be found in the Xilinx Zynq-7000 All Programmable SoC,[16] which includes a 1.0 GHz dual-core ARM Cortex-A9 MPCore processor embedded within the FPGA's logic fabric[17] or in the Altera Arria V FPGA, which includes an 800 MHz dual-core ARM Cortex-A9 MPCore. The Atmel FPSLIC is another such device, which uses an AVR processor in combination with Atmel's programmable logic architecture. The Microsemi SmartFusion devices incorporate an ARM Cortex-M3 hard processor core (with up to 512 kB of flash and 64 kB of RAM) and analog peripherals such as a multi-channel analog-to-digital converters and digital-to-analog converters to their flash memory-based FPGA fabric.

Xilinx Zynq-7000 AP SoC
A Xilinx Zynq-7000 All Programmable System on a Chip.

An alternate approach to using hard-macro processors is to make use of soft processor IP cores that are implemented within the FPGA logic. Nios II, MicroBlaze and Mico32 are examples of popular softcore processors. Many modern FPGAs are programmed at "run time", which has led to the idea of reconfigurable computing or reconfigurable systems – CPUs that reconfigure themselves to suit the task at hand. Additionally, new, non-FPGA architectures are beginning to emerge. Software-configurable microprocessors such as the Stretch S5000 adopt a hybrid approach by providing an array of processor cores and FPGA-like programmable cores on the same chip.

Companies like Microsoft have started to use FPGAs to accelerate high-performance, computationally intensive systems (like the data centers that operate their Bing search engine), due to the performance per watt advantage FPGAs deliver.[18] Microsoft began using FPGAs to accelerate Bing in 2014, and in 2018 began deploying FPGAs across other data center workloads for their Azure cloud computing platform.[19]

Timelines

Gates

  • 1987: 9,000 gates, Xilinx[10]
  • 1992: 600,000, Naval Surface Warfare Department[7]
  • Early 2000s: Millions[15]
  • 2013: 50 Million, Xilinx[20]

Market size

  • 1985: First commercial FPGA : Xilinx XC2064[9][10]
  • 1987: $14 million[10]
  • ≈1993: >$385 million[10]
  • 2005: $1.9 billion[21]
  • 2010 estimates: $2.75 billion[21]
  • 2013: $5.4 billion[22]
  • 2020 estimate: $9.8 billion[22]

Design starts

A design start is a new custom design for implementation on an FPGA.

Comparisons

To ASICs

Historically, FPGAs have been slower, less energy efficient and generally achieved less functionality than their fixed ASIC counterparts. An older study showed that designs implemented on FPGAs need on average 40 times as much area, draw 12 times as much dynamic power, and run at one third the speed of corresponding ASIC implementations.

More recently, FPGAs such as the Xilinx Virtex-7 or the Altera Stratix 5 have come to rival corresponding ASIC and ASSP ("Application-specific standard part", such as a standalone USB interface chip[25]) solutions by providing significantly reduced power usage, increased speed, lower materials cost, minimal implementation real-estate, and increased possibilities for re-configuration 'on-the-fly'. Where previously a design may have included 6 to 10 ASICs, the same design can now be achieved using only one FPGA.[26]

Advantages of FPGAs include the ability to re-program when already deployed (i.e. "in the field") to fix bugs, and often include shorter time to market and lower non-recurring engineering costs. Vendors can also take a middle road via FPGA prototyping: developing their prototype hardware on FPGAs, but manufacture their final version as an ASIC so that it can no longer be modified after the design has been committed.

Trends

Xilinx claimed that several market and technology dynamics are changing the ASIC/FPGA paradigm as of February 2009:[27]

  • Integrated circuit development costs were rising aggressively
  • ASIC complexity has lengthened development time
  • R&D resources and headcount were decreasing
  • Revenue losses for slow time-to-market were increasing
  • Financial constraints in a poor economy were driving low-cost technologies.

These trends make FPGAs a better alternative than ASICs for a larger number of higher-volume applications than they have been historically used for, to which the company attributes the growing number of FPGA design starts (see § History).[27]

Some FPGAs have the capability of partial re-configuration that lets one portion of the device be re-programmed while other portions continue running.[28][29]

Complex programmable logic devices (CPLD)

The primary differences between complex programmable logic devices (CPLDs) and FPGAs are architectural. A CPLD has a comparatively restrictive structure consisting of one or more programmable sum-of-products logic arrays feeding a relatively small number of clocked registers. As a result, CPLDs are less flexible, but have the advantage of more predictable timing delays and a higher logic-to-interconnect ratio. FPGA architectures, on the other hand, are dominated by interconnect. This makes them far more flexible (in terms of the range of designs that are practical for implementation on them) but also far more complex to design for, or at least requiring more complex electronic design automation (EDA) software.

In practice, the distinction between FPGAs and CPLDs is often one of size as FPGAs are usually much larger in terms of resources than CPLDs. Typically only FPGAs contain more complex embedded functions such as adders, multipliers, memory, and serializer/deserializers. Another common distinction is that CPLDs contain embedded flash memory to store their configuration while FPGAs usually require external non-volatile memory (but not always).

When a design requires simple instant-on (logic is already configured at power-up) CPLDs are generally preferred. For most other applications FPGAs are generally preferred. Sometimes both CPLDs and FPGAs are used in a single system design. In those designs, CPLDs generally perform glue logic functions, and are responsible for “booting” the FPGA as well as controlling reset and boot sequence of the complete circuit board. Therefore, depending on the application it may be judicious to use both FPGAs and CPLDs in a single design.[30]

Security considerations

FPGAs have both advantages and disadvantages as compared to ASICs or secure microprocessors, concerning hardware security. FPGAs' flexibility makes malicious modifications during fabrication a lower risk.[31] Previously, for many FPGAs, the design bitstream was exposed while the FPGA loads it from external memory (typically on every power-on). All major FPGA vendors now offer a spectrum of security solutions to designers such as bitstream encryption and authentication. For example, Altera and Xilinx offer AES encryption (up to 256-bit) for bitstreams stored in an external flash memory.

FPGAs that store their configuration internally in nonvolatile flash memory, such as Microsemi's ProAsic 3 or Lattice's XP2 programmable devices, do not expose the bitstream and do not need encryption. In addition, flash memory for a lookup table provides single event upset protection for space applications. Customers wanting a higher guarantee of tamper resistance can use write-once, antifuse FPGAs from vendors such as Microsemi.

With its Stratix 10 FPGAs and SoCs, Altera introduced a Secure Device Manager and physically uncloneable functions to provide high levels of protection against physical attacks.[32]

In 2012 researchers Sergei Skorobogatov and Christopher Woods demonstrated that FPGAs can be vulnerable to hostile intent. They discovered a critical backdoor vulnerability had been manufactured in silicon as part of the Actel/Microsemi ProAsic 3 making it vulnerable on many levels such as reprogramming crypto and access keys, accessing unencrypted bitstream, modifying low-level silicon features, and extracting configuration data.[33]

Applications

An FPGA can be used to solve any problem which is computable. This is trivially proven by the fact that FPGAs can be used to implement a soft microprocessor, such as the Xilinx MicroBlaze or Altera Nios II. Their advantage lies in that they are significantly faster for some applications because of their parallel nature and optimality in terms of the number of gates used for certain processes.[34]

FPGAs originally began as competitors to CPLDs to implement glue logic for printed circuit boards. As their size, capabilities, and speed increased, FPGAs took over additional functions to the point where some are now marketed as full systems on chips (SoCs). Particularly with the introduction of dedicated multipliers into FPGA architectures in the late 1990s, applications which had traditionally been the sole reserve of digital signal processor hardware (DSPs) began to incorporate FPGAs instead.[35][36]

Another trend in the use of FPGAs is hardware acceleration, where one can use the FPGA to accelerate certain parts of an algorithm and share part of the computation between the FPGA and a generic processor.[2] The search engine Bing is noted for adopting FPGA acceleration for its search algorithm in 2014.[37] As of 2018, FPGAs are seeing increased use as AI accelerators including Microsoft's so-termed "Project Catapult"[19] and for accelerating artificial neural networks for machine learning applications.

Traditionally, FPGAs have been reserved for specific vertical applications where the volume of production is small. For these low-volume applications, the premium that companies pay in hardware cost per unit for a programmable chip is more affordable than the development resources spent on creating an ASIC. As of 2017, new cost and performance dynamics have broadened the range of viable applications.

In Italy, the company Biomine srl has patented the application of FPGA processors, improving its yield in cryptocurrency mining

Common applications

Architecture

Logic blocks

FPGA cell example
Simplified example illustration of a logic cell (LUT - Lookup table, FA - Full adder, DFF - D-type flip-flop)

The most common FPGA architecture consists of an array of logic blocks,[note 1] I/O pads, and routing channels.[1] Generally, all the routing channels have the same width (number of wires). Multiple I/O pads may fit into the height of one row or the width of one column in the array.

An application circuit must be mapped into an FPGA with adequate resources. While the number of CLBs/LABs and I/Os required is easily determined from the design, the number of routing tracks needed may vary considerably even among designs with the same amount of logic.[note 2]

For example, a crossbar switch requires much more routing than a systolic array with the same gate count. Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit, FPGA manufacturers try to provide just enough tracks so that most designs that will fit in terms of lookup tables (LUTs) and I/Os can be routed.[note 2] This is determined by estimates such as those derived from Rent's rule or by experiments with existing designs. As of 2018, network-on-chip architectures for routing and interconnection are being developed.

In general, a logic block consists of a few logical cells (called ALM, LE, slice etc.). A typical cell consists of a 4-input LUT, a full adder (FA) and a D-type flip-flop, as shown above. The LUTs are in this figure split into two 3-input LUTs. In normal mode those are combined into a 4-input LUT through the left multiplexer (mux). In arithmetic mode, their outputs are fed to the adder. The selection of mode is programmed into the middle MUX. The output can be either synchronous or asynchronous, depending on the programming of the mux to the right, in the figure example. In practice, entire or parts of the adder are stored as functions into the LUTs in order to save space.[40][41][42]

Hard blocks

Modern FPGA families expand upon the above capabilities to include higher level functionality fixed in silicon. Having these common functions embedded in the circuit reduces the area required and gives those functions increased speed compared to building them from logical primitives. Examples of these include multipliers, generic DSP blocks, embedded processors, high speed I/O logic and embedded memories.

Higher-end FPGAs can contain high speed multi-gigabit transceivers and hard IP cores such as processor cores, Ethernet medium access control units, PCI/PCI Express controllers, and external memory controllers. These cores exist alongside the programmable fabric, but they are built out of transistors instead of LUTs so they have ASIC-level performance and power consumption without consuming a significant amount of fabric resources, leaving more of the fabric free for the application-specific logic. The multi-gigabit transceivers also contain high performance analog input and output circuitry along with high-speed serializers and deserializers, components which cannot be built out of LUTs. Higher-level PHY layer functionality such as line coding may or may not be implemented alongside the serializers and deserializers in hard logic, depending on the FPGA.

Clocking

Most of the circuitry built inside of an FPGA is synchronous circuitry that requires a clock signal. FPGAs contain dedicated global and regional routing networks for clock and reset so they can be delivered with minimal skew. Also, FPGAs generally contain analog phase-locked loop and/or delay-locked loop components to synthesize new clock frequencies as well as attenuate jitter. Complex designs can use multiple clocks with different frequency and phase relationships, each forming separate clock domains. These clock signals can be generated locally by an oscillator or they can be recovered from a high speed serial data stream. Care must be taken when building clock domain crossing circuitry to avoid metastability. FPGAs generally contain block RAMs that are capable of working as dual port RAMs with different clocks, aiding in the construction of building FIFOs and dual port buffers that connect differing clock domains.

3D architectures

To shrink the size and power consumption of FPGAs, vendors such as Tabula and Xilinx have introduced 3D or stacked architectures.[43][44] Following the introduction of its 28 nm 7-series FPGAs, Xilinx said that several of the highest-density parts in those FPGA product lines will be constructed using multiple dies in one package, employing technology developed for 3D construction and stacked-die assemblies.

Xilinx's approach stacks several (three or four) active FPGA dies side-by-side on a silicon interposer – a single piece of silicon that carries passive interconnect.[44][45] The multi-die construction also allows different parts of the FPGA to be created with different process technologies, as the process requirements are different between the FPGA fabric itself and the very high speed 28 Gbit/s serial transceivers. An FPGA built in this way is called a heterogeneous FPGA.[46]

Altera's heterogeneous approach involves using a single monolithic FPGA die and connecting other die/technologies to the FPGA using Intel's embedded multi-die interconnect bridge (EMIB) technology.[47]

Design and programming

To define the behavior of the FPGA, the user provides a design in a hardware description language (HDL) or as a schematic design. The HDL form is more suited to work with large structures because it's possible to specify high-level functional behavior rather than drawing every piece by hand. However, schematic entry can allow for easier visualization of a design and its component modules.

Using an electronic design automation tool, a technology-mapped netlist is generated. The netlist can then be fit to the actual FPGA architecture using a process called place-and-route, usually performed by the FPGA company's proprietary place-and-route software. The user will validate the map, place and route results via timing analysis, simulation, and other verification and validation methodologies. Once the design and validation process is complete, the binary file generated, typically using the FPGA vendor's proprietary software, is used to (re-)configure the FPGA. This file is transferred to the FPGA/CPLD via a serial interface (JTAG) or to an external memory device like an EEPROM.

The most common HDLs are VHDL and Verilog as well as extensions such as SystemVerilog. However, in an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of assembly languages, there are moves to raise the abstraction level through the introduction of alternative languages. National Instruments' LabVIEW graphical programming language (sometimes referred to as "G") has an FPGA add-in module available to target and program FPGA hardware.

To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. These predefined circuits are commonly called intellectual property (IP) cores, and are available from FPGA vendors and third-party IP suppliers. They are rarely free, and typically released under proprietary licenses. Other predefined circuits are available from developer communities such as OpenCores (typically released under free and open source licenses such as the GPL, BSD or similar license), and other sources. Such designs are known as "open-source hardware."

In a typical design flow, an FPGA application developer will simulate the design at multiple stages throughout the design process. Initially the RTL description in VHDL or Verilog is simulated by creating test benches to simulate the system and observe results. Then, after the synthesis engine has mapped the design to a netlist, the netlist is translated to a gate-level description where simulation is repeated to confirm the synthesis proceeded without errors. Finally the design is laid out in the FPGA at which point propagation delays can be added and the simulation run again with these values back-annotated onto the netlist.

More recently, OpenCL (Open Computing Language) is being used by programmers to take advantage of the performance and power efficiencies that FPGAs provide. OpenCL allows programmers to develop code in the C programming language and target FPGA functions as OpenCL kernels using OpenCL constructs.[48] For further information, see high-level synthesis and C to HDL.

Basic process technology types

  • SRAM – based on static memory technology. In-system programmable and re-programmable. Requires external boot devices. CMOS. Currently in use. Notably, flash memory or EEPROM devices may often load contents into internal SRAM that controls routing and logic.
  • Fuse – One-time programmable. Bipolar. Obsolete.
  • Antifuse – One-time programmable. CMOS.
  • PROM – Programmable Read-Only Memory technology. One-time programmable because of plastic packaging. Obsolete.
  • EPROM – Erasable Programmable Read-Only Memory technology. One-time programmable but with window, can be erased with ultraviolet (UV) light. CMOS. Obsolete.
  • EEPROM – Electrically Erasable Programmable Read-Only Memory technology. Can be erased, even in plastic packages. Some but not all EEPROM devices can be in-system programmed. CMOS.
  • Flash – Flash-erase EPROM technology. Can be erased, even in plastic packages. Some but not all flash devices can be in-system programmed. Usually, a flash cell is smaller than an equivalent EEPROM cell and is therefore less expensive to manufacture. CMOS.

Major manufacturers

In 2016, long-time industry rivals Xilinx and Altera (now an Intel subsidiary) were the FPGA market leaders.[49] At that time, they controlled nearly 90 percent of the market.

Both Xilinx and Altera[note 3] provide proprietary electronic design automation software for Windows and Linux (ISE/Vivado and Quartus) which enables engineers to design, analyze, simulate, and synthesize (compile) their designs.[50][51]

Other manufacturers include:

  • Microchip:
    • Microsemi (previously Actel), producing antifuse, flash-based, mixed-signal FPGAs; acquired by Microchip in 2018
    • Atmel, a second source of some Altera-compatible devices; also FPSLIC mentioned above;[52] acquired by Microchip in 2016
  • Lattice Semiconductor, which manufactures low-power SRAM-based FPGAs featuring integrated configuration flash, instant-on and live reconfiguration
  • QuickLogic,[53] which manufactures Ultra Low Power Sensor Hubs, extremely low powered, low density SRAM-based FPGAs, with display bridges MIPI & RGB inputs, MIPI, RGB and LVDS outputs
  • Achronix, manufacturing SRAM based FPGAS with 1.5 GHz fabric speed[54]

In March 2010, Tabula announced their FPGA technology that uses time-multiplexed logic and interconnect that claims potential cost savings for high-density applications.[55] On March 24, 2015, Tabula officially shut down.[56]

On June 1, 2015, Intel announced it would acquire Altera for approximately $16.7 billion and completed the acquisition on December 30, 2015.[57]

See also

Notes

  1. ^ Called configurable logic block (CLB) or logic array block (LAB), depending on vendor
  2. ^ a b For more information, see routing in electronic design automation, as part of the place and route step of integrated circuit manufacturing.
  3. ^ now Intel

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  55. ^ "Tabula's Time Machine — Micro Processor Report" (PDF). Archived from the original (PDF) on 2011-04-10.
  56. ^ Tabula to shut down; 120 jobs lost at fabless chip company Silicon Valley Business Journal
  57. ^ "Intel to buy Altera for $16.7 billion in its biggest deal ever". Reuters. June 2015.

Further reading

  • Sadrozinski, Hartmut F.-W.; Wu, Jinyuan (2010). Applications of Field-Programmable Gate Arrays in Scientific Research. Taylor & Francis. ISBN 978-1-4398-4133-4.
  • Wirth, Niklaus (1995). Digital Circuit Design An Introduction Textbook. Springer. ISBN 978-3-540-58577-0.

External links

Amber (processor core)

The Amber processor core is an ARM architecture-compatible 32-bit reduced instruction set computing (RISC) processor. It is open source, hosted on the OpenCores website, and is part of a movement to develop a library of open source hardware projects.

C to HDL

C to HDL tools convert C language or C-like computer code into a hardware description language (HDL) such as VHDL or Verilog. The converted code can then be synthesized and translated into a hardware device such as a field-programmable gate array. Compared to software, equivalent designs in hardware consume less power (yielding higher performance per watt) and execute faster with lower latency, more parallelism and higher throughput. However, system design and functional verification in a hardware description language can be tedious and time-consuming, so systems engineers often write critical modules in HDL and other modules in a high-level language and synthesize these into HDL through C to HDL or high-level synthesis tools.

C to RTL is another name for this methodology. RTL refers to the register transfer level representation of a program necessary to implement it in logic.

Computing with Memory

Computing with Memory refers to computing platforms where function response is stored in memory array, either one or two-dimensional, in the form of lookup tables (LUTs) and functions are evaluated by retrieving the values from the LUTs. These computing platforms can follow either a purely spatial computing model, as in field-programmable gate array (FPGA), or a temporal computing model, where a function is evaluated across multiple clock cycles. The latter approach aims at reducing the overhead of programmable interconnect in FPGA by folding interconnect resources inside a computing element. It uses dense two-dimensional memory arrays to store large multiple-input multiple-output LUTs. Computing with Memory differs from Computing in Memory or processor-in-memory (PIM) concepts, widely investigated in the context of integrating a processor and memory on the same chip to reduce memory latency and increase bandwidth. These architectures seek to reduce the distance the data travels between the processor and the memory. The Berkeley IRAM project is one notable contribution in the area of PIM architectures.

Embedded System Module

Embedded System Module, or ESM, is a compact computer-on-module (COM) standard. An ESM module typically includes a CPU processor, memory, module-specific I/O interfaces and a number of basic front I/O connectors. They can be plugged on a carrier board or be used as a stand-alone processor card.

If the ESM module is plugged on a carrier, it relies on the standard PCI bus as a board-to-board interface. In this case two connectors create a link to the carrier. While the "J1" connector provides a specified PCI connection, the "J2" connector brings I/O signals from the ESM module to the carrier, which then includes all necessary connectors. The signal assignment of J2 is not fixed but can be completely customized, although there are reserved pins for a 64-bit PCI bus interface. A third connector, "J3", is used for additional I/O signals if the ESM module has no front I/O. The signal assignment of this connector is fixed to support a special set of I/O functions.

A large part of the I/O functions on ESMs are often controlled by an onboard FPGA component (field-programmable gate array) so that every module can easily be tailored to a specialized application through user-defined functions. Such functions are loaded into the FPGA as IP cores. Using FPGAs also reduces dependence on special controller chips which may become obsolete, thus extending the card's availability.

ESMs are typically used on boards for CompactPCI and VMEbus as well as single-board computers for embedded applications. A company standard by MEN Micro, a manufacturer of embedded computers, specifies the ESM concept and the different types of modules. The ESM specification defines one form factor for the printed circuit board: 149 × 71 mm (5.9 × 2.8 in).

Depending on the processor type, most ESM modules have heat sinks and can be operated in wide temperature ranges up to -40 to +85 °C.

A mechanical specialty of ESM modules is that their connectors are compatible with the PCI-104 module standard. These modules can be "stacked" onto ESM modules, e. g., for additional peripheral interfaces.

Field-programmable RF

The field-programmable RF (FPRF) is a class of radio frequency transceiver microchip that mimics the concept of an FPGA (field programmable gate array) in the radio frequency domain to deliver a multi-standard, multi frequency device.

The earliest use of the term comes from Wireless Design Mag and it has subsequently been used by a wide range of electronics trade magazines to describe the emerging class of multi frequency and multi standard flexible RF chips.

Field Programmable Nanowire Interconnect

Field Programmable Nanowire Interconnect (often abbreviated FPNI) is a new computer architecture developed by Hewlett-Packard. This is a defect-tolerant architecture, using the results of the Teramac experiment.

Details:

The design combines a nanoscale crossbar switch structure with conventional CMOS to create a hybrid chip that is simpler to fabricate and offers greater flexibility in the choice of nanoscale devices. The FPNI improves on a field-programmable gate array (FPGA) architecture by lifting the configuration bit and associated components out of the semiconductor plane and replacing them in the interconnect with nonvolatile switches, which decreases both the area and power consumption of the circuit -- while providing up to eight times the density at less cost. This is an example of a more comprehensive strategy for improving the efficiency of existing semiconductor technology: placing a level of intelligence and configurability in the interconnect can have a profound effect on integrated circuit performance, and can be used to significantly extend Moore's Law without having to shrink the transistors.

Flow to HDL

Flow to HDL tools and methods convert flow-based system design into a hardware description language (HDL) such as VHDL or Verilog. Typically this is a method of creating designs for field-programmable gate array, application-specific integrated circuit prototyping and digital signal processing (DSP) design. Flow-based system design is well-suited to field-programmable gate array design as it is easier to specify the innate parallelism of the architecture.

Logic block

In computing, a logic block or configurable logic block (CLB) is a fundamental building block of field-programmable gate array (FPGA) technology. Logic blocks can be configured by the engineer to provide reconfigurable logic gates.

Logic blocks are the most common FPGA architecture, and are usually laid out within a logic block array. Logic blocks require I/O pads (to interface with external signals), and routing channels (to interconnect logic blocks).

Programmable logic blocks were invented by David W. Page and LuVerne R. Peterson, and defined within their 1985 patents.

Minimig

Minimig (short for Mini Amiga) is an open source re-implementation of an Amiga 500 using a field-programmable gate array (FPGA).

Minimig started around January 2005 as a proof of concept by Dutch electrical engineer Dennis van Weeren. He intended Minimig as the answer to the ongoing discussions within the Amiga community on implementing the Amiga custom chipset using an FPGA. The project's source code and schematics were released under version 3 of the GNU General Public Licence on 25 July 2007.

Nallatech

Nallatech is a computer hardware and software firm based in Camarillo, California, United States

The company specializes in field-programmable gate array (FPGA) integrated circuit technology applied in computing. As of 2007 the company's primary markets were defense and high-performance computing.Nallatech was acquired by Interconnect Systems, Inc. in 2008,

which in turn was bought by Molex in 2016.

Negai (satellite)

Negai☆″ ("Wish") is a Japanese satellite which launched in May 2010. It is a student-built spacecraft, which will be operated by Soka University, and is intended to be used for technology demonstration. The satellite is a single unit CubeSat, and will be used to test a field programmable gate array in orbit. As part of an outreach programme, it will carry the names of selected children, along with wishes they have made. The satellite will return images of the Earth, which will be given to the participating children.The launch was conducted by Mitsubishi Heavy Industries under contract to the Japan Aerospace Exploration Agency. In preparation for a planned launch on 17 May, the H-IIA rocket was rolled out to Pad 1 of the Yoshinobu Launch Complex at the Tanegashima Space Centre on 16 May 2010. It departed the assembly building at 21:01 UTC and arriving at the launch pad 24 minutes later at 21:25 UTC. The terminal countdown began at 11:30 UTC on 17 May and by 15:28, the loading of cryogenic propellant into the rocket's first and second stages had been completed. The launch attempt was scrubbed a few minutes before liftoff due to bad weather, but took place successfully at 21:58:22 UTC on 20 May 2010.

Negai was deployed from a JAXA Picosatellite Deployer attached to the second stage of the H-IIA 202 rocket used in the launch of the Akatsuki spacecraft towards Venus. Negai shared its dispenser with the K-Sat satellite, whilst a second dispenser contained Waseda-SAT2. The three CubeSats separated into low Earth orbit during a coast phase of the launch, between the first and second burns of the second stage. The rocket then continued to Heliocentric orbit, where it deployed Akatsuki, along with the IKAROS and UNITEC-1 spacecraft.

Nios II

Nios II is a 32-bit embedded-processor architecture designed specifically for the Altera family of field-programmable gate array (FPGA) integrated circuits. Nios II incorporates many enhancements over the original Nios architecture, making it more suitable for a wider range of embedded computing applications, from digital signal processing (DSP) to system-control.

Nios II is a successor to Altera's first configurable 16-bit embedded processor Nios.

Place and route

Place and route is a stage in the design of printed circuit boards, integrated circuits, and field-programmable gate arrays. As implied by the name, it is composed of two steps, placement and routing. The first step, placement, involves deciding where to place all electronic components, circuitry, and logic elements in a generally limited amount of space. This is followed by routing, which decides the exact design of all the wires needed to connect the placed components. This step must implement all the desired connections while following the rules and limitations of the manufacturing process.

Place and route is used in several contexts:

Printed circuit boards, during which components are graphically placed on the board and the wires drawn between them

Integrated circuits, during which a layout of a larger block of the circuit or the whole circuit is created from layouts of smaller sub-blocks

FPGAs, during which logic elements are placed and interconnected on the grid of the FPGAThese processes are similar at a high level, but the actual details are very different. With the large sizes of modern designs, this operation is usually performed by electronic design automation (EDA) tools.

In all these contexts, the final result when placing and routing is finished is the layout,

a geometric description of the location and rotation of each part, and the exact path of each wire connecting them.

Occasionally some people call the entire place-and-route process layout.

Power integrity

Power integrity or PI is an analysis to check whether the desired voltage and current are met from source to destination. Today, power integrity plays a major role in the success and failure of new electronic products. There are several coupled aspects of PI: on the chip, in the chip package, on the circuit board, and in the system. Four main issues must be resolved to ensure power integrity at the printed circuit board level:

Keep the voltage ripple at the chips pads lower than the specification (e.g. less than +/-50 mV variation around 1V)

Control ground bounce (also called synchronous switching noise, simultaneous switching noise, or simultaneous switching output (SSN or SSO))

Control electromagnetic interference and maintain electromagnetic compatibility: the power distribution network is generally the largest set of conductors on the circuit board and therefore the largest (unwanted) antenna for emission and reception of noise.

Maintaining a proper DC Voltage level at the load at high currents. A modern processor or field-programmable gate array can pull 1-100 Amps at sub-1V VDD levels with AC and DC margins in the tens of millivolts. Very litle DC voltage drop can thus be tolerated on the power distribution network.

Scott Hauck

Scott Hauck is an electrical engineer from the University of Washington in Seattle. He was named a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 2016 for his contributions to field-programmable gate array-based systems.

Tarari

Tarari is a company that spun out of Intel in 2002 [1]. It has created a range of re-programmable silicon based on Xilinx[2] Virtex-4 FPGA (Field Programmable Gate Array) and ASICs [3] that offload and accelerate really complex algorithms such as XML Parsing, scanning for Computer viruses, email spam and intruders in Intrusion-prevention systems and Unified threat management appliances. As well as inspecting content its Content Processors can also transform content and they are used for XML transformation XSLT, compression, encryption as well as HD Video encoding for WMV and VC-1 formats.

In June 2006, Tarari announced that its next generation chips that will support the AMD Torrenza [4] initiative - and it will incorporate HyperTransport [5] interfaces. HyperTransport based-systems offer a dramatically reduced latency and increased throughput. This is because a HyperTransport connected system allows a co-processor to have direct access to the system's HyperTransport bus, and thus as much access to system resources as other conventional CPUs.

PCI-Express and HyperTransport buses both allow systems to communicate at 20-25 Gbit/s versus 4-8 Gbit/s for Peripheral Component Interconnect PCI/PCI-X based systems. Just as the latest desktop machines are using PCI-Express for their high-performance graphic cards now servers will be able to use these high speed interconnects to add other hardware-based co-processors.

PCI-Express and HyperTransport buses both operate serially using multiple lanes - PCI-Express supports 1, 2, 4 or 8 lane connectivity at 2.5 Gbit/s per lane. Whereas PCI/PCI-X works using parallel transfers and is most efficient in the 2k - 4k byte per transfer range, PCI-Express and HyperTransport are very efficient at transfers as small as just 64 bytes. Therefore, applications such as in intrusion-prevention system (IPS) and VOIP security applications which have to examine a large volume of small packets will benefit from such high-speed and highly efficient transfer capabilities.

On 5 September 2007, LSI Corporation announced a definitive agreement to acquire Tarari.

Telematic control unit

A telematic control unit (TCU) in the automobile industry refers to the embedded system on board of a vehicle that controls tracking of the vehicle.

A TCU consists of:

a global positioning system (GPS) unit, which keeps track of the latitude and longitude values of the vehicle;

an external interface for mobile communication (GSM, GPRS, Wi-Fi, WiMax, or LTE), which provides the tracked values to a centralized geographical information system (GIS) database server;

an electronic processing unit;

a microcontroller, in some versions; a microprocessor or field programmable gate array (FPGA), which processes the information and acts on the interface between the GPS;

a mobile communication unit;

and some amount of memory for saving GPS values in case of mobile-free zones or to intelligently store information about the vehicle's sensor data.

XBC

The XBC, or the Xport Botball Controller, is a robot based on Charmed Labs' Xport hardware. It was built specifically for the Botball competition and uses a Game Boy Advance for its display and for high-level processing; a field-programmable gate array is used to offload low-level processing of motors and sensors from the Game Boy Advance. The XBC is programmed using Interactive C, which is a variant of the C programming language. The XBC replaced the RCX in 2005 as Botball's official processor. The RCX can be programmed using Interactive C, Not Quite C, or Lego's simple GUI interface. Both robots can have bases built with Lego pieces.

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