Complementary metal–oxide–semiconductor (CMOS) is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors (CMOS sensor), data converters, and highly integrated transceivers for many types of communication. Frank Wanlass patented CMOS in 1963 (US patent 3,356,858) while working for Fairchild Semiconductor.

CMOS is also sometimes referred to as complementary-symmetry metal–oxide–semiconductor (COS-MOS).[1] The words "complementary-symmetry" refer to the typical design style with CMOS using complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions.[2]

Two important characteristics of CMOS devices are high noise immunity and low static power consumption.[3] Since one transistor of the pair is always off, the series combination draws significant power only momentarily during switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor–transistor logic (TTL) or N-type metal-oxide-semiconductor logic (NMOS) logic, which normally have some standing current even when not changing state. CMOS also allows a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most used technology to be implemented in very-large-scale integration (VLSI) chips.

The phrase "metal–oxide–semiconductor" is a reference to the physical structure of certain field-effect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor material. Aluminium was once used but now the material is polysilicon. Other metal gates have made a comeback with the advent of high-κ dielectric materials in the CMOS process, as announced by IBM and Intel for the 45 nanometer node and smaller sizes.[4]

CMOS inverter
CMOS inverter (a NOT logic gate)

Technical details

"CMOS" refers to both a particular style of digital circuitry design and the family of processes used to implement that circuitry on integrated circuits (chips). CMOS circuitry dissipates less power than logic families with resistive loads. Since this advantage has increased and grown more important, CMOS processes and variants have come to dominate, thus the vast majority of modern integrated circuit manufacturing is on CMOS processes.[5] As of 2010, CPUs with the best performance per watt each year have been CMOS static logic since 1976.

CMOS circuits use a combination of p-type and n-type metal–oxide–semiconductor field-effect transistor (MOSFETs) to implement logic gates and other digital circuits. Although CMOS logic can be implemented with discrete devices for demonstrations, commercial CMOS products are integrated circuits composed of up to billions of transistors of both types, on a rectangular piece of silicon of between 10 and 400 mm2.

CMOS always uses all enhancement-mode MOSFETs (in other words, a zero gate-to-source voltage turns the transistor off).


CMOS circuits are constructed in such a way that all P-type metal-oxide-semiconductor (PMOS) transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors must have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates low resistance between its source and drain contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied. CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET not to conduct, while a low voltage on the gates causes the reverse. This arrangement greatly reduces power consumption and heat generation. However, during the switching time, both MOSFETs conduct briefly as the gate voltage goes from one state to another. This induces a brief spike in power consumption and becomes a serious issue at high frequencies.

CMOS Inverter
Static CMOS inverter. Vdd and Vss are standing for drain and source respectively.

The adjacent image shows what happens when an input is connected to both a PMOS transistor (top of diagram) and an NMOS transistor (bottom of diagram). When the voltage of input A is low, the NMOS transistor's channel is in a high resistance state. This limits the current that can flow from Q to ground. The PMOS transistor's channel is in a low resistance state and much more current can flow from the supply to the output. Because the resistance between the supply voltage and Q is low, the voltage drop between the supply voltage and Q due to a current drawn from Q is small. The output, therefore, registers a high voltage.

On the other hand, when the voltage of input A is high, the PMOS transistor is in an OFF (high resistance) state so it would limit the current flowing from the positive supply to the output, while the NMOS transistor is in an ON (low resistance) state, allowing the output from drain to ground. Because the resistance between Q and ground is low, the voltage drop due to a current drawn into Q placing Q above ground is small. This low drop results in the output registering a low voltage.

In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output is high, and when the input is high, the output is low. Because of this behavior of input and output, the CMOS circuit's output is the inverse of the input.

Power supply pins

The power supply pins for CMOS are called VDD and VSS, or VCC and Ground(GND) depending on the manufacturer. VDD and VSS are carryovers from conventional MOS circuits and stand for the drain and source supplies.[6] These do not apply directly to CMOS, since both supplies are really source supplies. VCC and Ground are carryovers from TTL logic and that nomenclature has been retained with the introduction of the 54C/74C line of CMOS.


An important characteristic of a CMOS circuit is the duality that exists between its PMOS transistors and NMOS transistors. A CMOS circuit is created to allow a path always to exist from the output to either the power source or ground. To accomplish this, the set of all paths to the voltage source must be the complement of the set of all paths to ground. This can be easily accomplished by defining one in terms of the NOT of the other. Due to the De Morgan's laws based logic, the PMOS transistors in parallel have corresponding NMOS transistors in series while the PMOS transistors in series have corresponding NMOS transistors in parallel.


NAND gate in CMOS logic

More complex logic functions such as those involving AND and OR gates require manipulating the paths between gates to represent the logic. When a path consists of two transistors in series, both transistors must have low resistance to the corresponding supply voltage, modelling an AND. When a path consists of two transistors in parallel, either one or both of the transistors must have low resistance to connect the supply voltage to the output, modelling an OR.

Shown on the right is a circuit diagram of a NAND gate in CMOS logic. If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low. If both of the A and B inputs are low, then neither of the NMOS transistors will conduct, while both of the PMOS transistors will conduct, establishing a conductive path between the output and Vdd (voltage source), bringing the output high. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and Vdd (voltage source), bringing the output high. As the only configuration of the two inputs that results in a low output is when both are high, this circuit implements a NAND (NOT AND) logic gate.

An advantage of CMOS over NMOS logic is that both low-to-high and high-to-low output transitions are fast since the (PMOS) pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full voltage between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise.

See Logical effort for a method of calculating delay in a CMOS circuit.

Example: NAND gate in physical layout

The physical layout of a NAND circuit. The larger regions of N-type diffusion and P-type diffusion are part of the transistors. The two smaller regions on the left are taps to prevent latchup.
CMOS fabrication process
Simplified process of fabrication of a CMOS inverter on p-type substrate in semiconductor microfabrication. Note: Gate, source and drain contacts are not normally in the same plane in real devices, and the diagram is not to scale.

This example shows a NAND logic device drawn as a physical representation as it would be manufactured. The physical layout perspective is a "bird's eye view" of a stack of layers. The circuit is constructed on a P-type substrate. The polysilicon, diffusion, and n-well are referred to as "base layers" and are actually inserted into trenches of the P-type substrate. (See steps 1 to 6 in the process diagram below right) The contacts penetrate an insulating layer between the base layers and the first layer of metal (metal1) making a connection.

The inputs to the NAND (illustrated in green color) are in polysilicon. The CMOS transistors (devices) are formed by the intersection of the polysilicon and diffusion; N diffusion for the N device & P diffusion for the P device (illustrated in salmon and yellow coloring respectively). The output ("out") is connected together in metal (illustrated in cyan coloring). Connections between metal and polysilicon or diffusion are made through contacts (illustrated as black squares). The physical layout example matches the NAND logic circuit given in the previous example.

The N device is manufactured on a P-type substrate while the P device is manufactured in an N-type well (n-well). A P-type substrate "tap" is connected to VSS and an N-type n-well tap is connected to VDD to prevent latchup.

Cmos impurity profile
Cross section of two transistors in a CMOS gate, in an N-well CMOS process

Power: switching and leakage

CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when switching ("dynamic power"). On a typical ASIC in a modern 90 nanometer process, switching the output might take 120 picoseconds, and happens once every ten nanoseconds. NMOS logic dissipates power whenever the transistor is on, because there is a current path from Vdd to Vss through the load resistor and the n-type network.

Static CMOS gates are very power efficient because they dissipate nearly zero power when idle. Earlier, the power consumption of CMOS devices was not the major concern while designing chips. Factors like speed and area dominated the design parameters. As the CMOS technology moved below sub-micron levels the power consumption per unit area of the chip has risen tremendously.

Broadly classifying, power dissipation in CMOS circuits occurs because of two components, static and dynamic:

Static dissipation

Both NMOS and PMOS transistors have a gate–source threshold voltage, below which the current (called sub threshold current) through the device drops exponentially. Historically, CMOS designs operated at supply voltages much larger than their threshold voltages (Vdd might have been 5 V, and Vth for both NMOS and PMOS might have been 700 mV). A special type of the CMOS transistor with near zero threshold voltage is the native transistor.

SiO2 is a good insulator, but at very small thickness levels electrons can tunnel across the very thin insulation; the probability drops off exponentially with oxide thickness. Tunnelling current becomes very important for transistors below 130 nm technology with gate oxides of 20 Å or thinner.

Small reverse leakage currents are formed due to formation of reverse bias between diffusion regions and wells (for e.g., p-type diffusion vs. n-well), wells and substrate (for e.g., n-well vs. p-substrate). In modern process diode leakage is very small compared to sub threshold and tunnelling currents, so these may be neglected during power calculations.

If the ratios do not match, then there might be different currents of PMOS and NMOS; this may lead to imbalance and thus improper current causes the CMOS to heat up and dissipate power unnecessarily.

Dynamic dissipation

Charging and discharging of load capacitances

CMOS circuits dissipate power by charging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. In one complete cycle of CMOS logic, current flows from VDD to the load capacitance to charge it and then flows from the charged load capacitance (CL) to ground during discharge. Therefore, in one complete charge/discharge cycle, a total of Q=CLVDD is thus transferred from VDD to ground. Multiply by the switching frequency on the load capacitances to get the current used, and multiply by the average voltage again to get the characteristic switching power dissipated by a CMOS device: .

Since most gates do not operate/switch at every clock cycle, they are often accompanied by a factor , called the activity factor. Now, the dynamic power dissipation may be re-written as .

A clock in a system has an activity factor α=1, since it rises and falls every cycle. Most data has an activity factor of 0.1.[7] If correct load capacitance is estimated on a node together with its activity factor, the dynamic power dissipation at that node can be calculated effectively.

Since there is a finite rise/fall time for both pMOS and nMOS, during transition, for example, from off to on, both the transistors will be on for a small period of time in which current will find a path directly from VDD to ground, hence creating a short-circuit current. Short-circuit power dissipation increases with rise and fall time of the transistors.

An additional form of power consumption became significant in the 1990s as wires on chip became narrower and the long wires became more resistive. CMOS gates at the end of those resistive wires see slow input transitions. During the middle of these transitions, both the NMOS and PMOS logic networks are partially conductive, and current flows directly from VDD to VSS. The power thus used is called crowbar power. Careful design which avoids weakly driven long skinny wires ameliorates this effect, but crowbar power can be a substantial part of dynamic CMOS power.

To speed up designs, manufacturers have switched to constructions that have lower voltage thresholds but because of this a modern NMOS transistor with a Vth of 200 mV has a significant subthreshold leakage current. Designs (e.g. desktop processors) which include vast numbers of circuits which are not actively switching still consume power because of this leakage current. Leakage power is a significant portion of the total power consumed by such designs. Multi-threshold CMOS (MTCMOS), now available from foundries, is one approach to managing leakage power. With MTCMOS, high Vth transistors are used when switching speed is not critical, while low Vth transistors are used in speed sensitive paths. Further technology advances that use even thinner gate dielectrics have an additional leakage component because of current tunnelling through the extremely thin gate dielectric. Using high-κ dielectrics instead of silicon dioxide that is the conventional gate dielectric allows similar device performance, but with a thicker gate insulator, thus avoiding this current. Leakage power reduction using new material and system designs is critical to sustaining scaling of CMOS.[8]

Input protection

Parasitic transistors that are inherent in the CMOS structure may be turned on by input signals outside the normal operating range, e.g. electrostatic discharges or line reflections. The resulting latch-up may damage or destroy the CMOS device. Clamp diodes are included in CMOS circuits to deal with these signals. Manufacturers' data sheets specify the maximum permitted current that may flow through the diodes.

Analog CMOS

Besides digital applications, CMOS technology is also used in analog applications. For example, there are CMOS operational amplifier ICs available in the market. Transmission gates may be used as analog multiplexers instead of signal relays. CMOS technology is also widely used for RF circuits all the way to microwave frequencies, in mixed-signal (analog+digital) applications.

Temperature range

Conventional CMOS devices work over a range of –55 °C to +125 °C.

There were theoretical indications as early as August 2008 that silicon CMOS will work down to –233 °C (40 K).[9] Functioning temperatures near 40 K have since been achieved using overclocked AMD Phenom II processors with a combination of liquid nitrogen and liquid helium cooling.[10]

Single-electron CMOS transistors

Ultra small (L = 20 nm, W = 20 nm) CMOS transistors achieve the single-electron limit when operated at cryogenic temperature over a range of –269 °C (4 K) to about –258 °C (15 K). The transistor displays Coulomb blockade due to progressive charging of electrons one by one. The number of electrons confined in the channel is driven by the gate voltage, starting from an occupation of zero electrons, and it can be set to one or many.[11]

See also


  1. ^ COS-MOS was an RCA trademark, which forced other manufacturers to find another name – CMOS
  2. ^ "What is CMOS Memory?". Wicked Sago. Archived from the original on 26 September 2014. Retrieved 3 March 2013.
  3. ^ Fairchild. Application Note 77. "CMOS, the Ideal Logic Family" Archived 2015-01-09 at the Wayback Machine. 1983.
  4. ^ "Intel® Architecture Leads the Microarchitecture Innovation Field". Intel. Archived from the original on 29 June 2011. Retrieved 2 May 2018.
  5. ^ Baker, R. Jacob (2008). CMOS: circuit design, layout, and simulation (Second ed.). Wiley-IEEE. p. xxix. ISBN 978-0-470-22941-5.
  6. ^ "Archived copy" (PDF). Archived (PDF) from the original on 2011-12-09. Retrieved 2011-11-25.CS1 maint: Archived copy as title (link)
  7. ^ K. Moiseev, A. Kolodny and S. Wimer, "Timing-aware power-optimal ordering of signals", ACM Transactions on Design Automation of Electronic Systems, Volume 13 Issue 4, September 2008, ACM
  8. ^ A good overview of leakage and reduction methods are explained in the book Leakage in Nanometer CMOS Technologies Archived 2011-12-02 at the Wayback Machine ISBN 0-387-25737-3.
  9. ^ Edwards C, "Temperature control", Engineering & Technology 26 July – 8 August 2008, IET
  10. ^ Patrick Moorhead (January 15, 2009). "Breaking Records with Dragons and Helium in the Las Vegas Desert". Archived from the original on September 15, 2010. Retrieved 2009-09-18.
  11. ^ Prati, E.; De Michielis, M.; Belli, M.; Cocco, S.; Fanciulli, M.; Kotekar-Patil, D.; Ruoff, M.; Kern, D. P.; Wharam, D. A.; Verduijn, J.; Tettamanzi, G. C.; Rogge, S.; Roche, B.; Wacquez, R.; Jehl, X.; Vinet, M.; Sanquer, M. (2012). "Few electron limit of n-type metal oxide semiconductor single electron transistors" (PDF). Nanotechnology. 23 (21): 215204. arXiv:1203.4811. Bibcode:2012Nanot..23u5204P. doi:10.1088/0957-4484/23/21/215204. PMID 22552118. Archived (PDF) from the original on 2014-10-04.

Further reading

External links

Active pixel sensor

An active-pixel sensor (APS) is an image sensor where each picture element ("pixel") has a photodetector and an active amplifier. There are many types of integrated circuit active pixel sensors including the complementary metal–oxide–semiconductor (CMOS) APS used most commonly in cell phone cameras, web cameras, most digital pocket cameras since 2010, in most digital single-lens reflex cameras (DSLRs) and Mirrorless interchangeable-lens cameras (MILCs). Such an image sensor is produced using CMOS technology (and is hence also known as a CMOS sensor), and has emerged as an alternative to charge-coupled device (CCD) image sensors.

The term 'active pixel sensor' is also used to refer to the individual pixel sensor itself, as opposed to the image sensor; in that case the image sensor is sometimes called an active pixel sensor imager, or active-pixel image sensor.

Back-illuminated sensor

A back-illuminated sensor, also known as backside illumination (BSI or BI) sensor, is a type of digital image sensor that uses a novel arrangement of the imaging elements to increase the amount of light captured and thereby improve low-light performance.

The technique was used for some time in specialized roles like low-light security cameras and astronomy sensors, but was complex to build and required further refinement to become widely used. Sony was the first to reduce these problems and their costs sufficiently to introduce a 5-megapixel 1.75 µm BI CMOS sensor at general consumer prices in 2009. BI sensors from OmniVision Technologies have since been used in consumer electronics from other manufacturers as in the HTC EVO 4G Android smartphone, and as a major selling point for the camera in Apple's iPhone 4.

Canon EOS 200D

The Canon EOS 200D, known as the EOS Rebel SL2 in the Americas and EOS Kiss X9 in Japan, is a 24.2-megapixel digital single-lens reflex camera made by Canon. It was announced on June 28, 2017 with a suggested retail price of $549 for the body and $699 with the Canon EF-S 18-55m f/4-5.6 IS STM lens. The European release price is significantly higher, at €599 for the body only, the equivalent of $671 at current conversion rates (but this price may include VAT).Its uses an APS-C CMOS sensor, Dual Pixel CMOS AF, DIGIC 7 image processor, ISO 100-25600 range, optical viewfinder with a 9-point AF system, 3.0-inch 1040k dot articulated touchscreen, 1080p60 video with microphone input, and built-in Wi-Fi, NFC and Bluetooth. It became available in July 2017 alongside Canon's parallel announcement of the 6D Mk II. It weighs 453 grams including battery and memory card.

Canon EOS 70D

The Canon EOS 70D is a digital single-lens reflex camera by Canon publicly announced on July 2, 2013 with a suggested retail price of $1,199. As a part of the Canon EOS two-digit line, it is the successor to the EOS 60D and is the predecessor of the EOS 80D.The EOS 70D is the launch platform for Canon's Dual Pixel CMOS Autofocus, which provides great improvement in focusing speed while in Live View, both for stills and video. At large apertures such as f/1.8, the 70D's Dual Pixel CMOS Autofocus provides a significant improvement in focus accuracy and consistency over conventional autofocus.The 70D can be purchased as a body alone, or in a package with an EF-S 18-55mm f/3.5-5.6 IS STM lens, EF-S 18-135mm f/3.5-5.6 IS STM lens, and/or EF-S 18-200mm f/3.5-5.6 IS lens.

The most recent available firmware is version 1.1.2.

Collateralized mortgage obligation

A collateralized mortgage obligation (CMO) is a type of complex debt security that repackages and directs the payments of principal and interest from a collateral pool to different types and maturities of securities, thereby meeting investor needs.CMOs were first created in 1983 by the investment banks Salomon Brothers and First Boston for the U.S. mortgage liquidity provider Freddie Mac. The Salomon Brothers team was led by Lewis Ranieri and the First Boston team by Laurence D. Fink, although Dexter Senft also later received an industry award for his contribution).

Legally, a CMO is a debt security issued by an abstraction—a special purpose entity—and is not a debt owed by the institution creating and operating the entity. The entity is the legal owner of a set of mortgages, called a pool. Investors in a CMO buy bonds issued by the entity, and they receive payments from the income generated by the mortgages according to a defined set of rules. With regard to terminology, the mortgages themselves are termed collateral, 'classes' refers to groups of mortgages issued to borrowers of roughly similar credit worthiness, tranches are specified fractions or slices, metaphorically speaking, of a pool of mortgages and the income they produce that are combined into an individual security, while the structure is the set of rules that dictates how the income received from the collateral will be distributed. The legal entity, collateral, and structure are collectively referred to as the deal. Unlike traditional mortgage pass-through securities, CMOs feature different payment streams and risks, depending on investor preferences. For tax purposes, CMOs are generally structured as Real Estate Mortgage Investment Conduits, which avoid the potential for "double-taxation".Investors in CMOs include banks, hedge funds, insurance companies, pension funds, mutual funds, government agencies, and most recently central banks. This article focuses primarily on CMO bonds as traded in the United States of America.

The term "collateralized mortgage obligation" technically refers to a security issued by a specific type of legal entity dealing in residential mortgages, but investors also frequently refer to deals put together using other types of entities such as real estate mortgage investment conduits as CMOs.

Comparison of Canon EOS digital cameras

The following tables provide general information as well as a comparison of technical specifications for a number of Canon EOS digital cameras.

Congressional caucus

A congressional caucus is a group of members of the United States Congress that meets to pursue common legislative objectives. Formally, caucuses are formed as congressional member organizations (CMOs) through the United States House of Representatives and the United States Senate and governed under the rules of these chambers. In addition to the term caucus, they are sometimes called conferences (especially Republican ones), coalitions, study groups, task forces, or working groups. Many other countries use the term parliamentary group—for example, the Parliament of the United Kingdom has many all-party parliamentary groups.


An EPROM (rarely EROM), or erasable programmable read-only memory, is a type of memory chip that retains its data when its power supply is switched off. Computer memory that can retrieve stored data after a power supply has been turned off and back on is called non-volatile. It is an array of floating-gate transistors individually programmed by an electronic device that supplies higher voltages than those normally used in digital circuits. Once programmed, an EPROM can be erased by exposing it to strong ultraviolet light source (such as from a mercury-vapor light). EPROMs are easily recognizable by the transparent fused quartz window in the top of the package, through which the silicon chip is visible, and which permits exposure to ultraviolet light during erasing.


Exmor is the name of a technology Sony implemented on some of their CMOS image sensors. It performs on-chip analog/digital signal conversion and two-step noise reduction in parallel on each column of the CMOS sensor.

Exmor R is a back-illuminated version of Sony's CMOS image sensor. Exmor R was announced by Sony on 11 June 2008 and was the world's first mass-produced implementation of the back-illuminated sensor technology Sony claims that Exmor R is approximately twice as sensitive as a normal front illuminated sensor. This active pixel sensor is found in several Sony mobile phones and cameras as well as Apple's iPhone 2G and 5. The Exmor R sensor allows the camera of the smartphone to capture high definition movies and stills in low light areas.

Originally, Exmor R was limited to smaller sensors for camcorders, compact cameras and mobile phones, but the Sony ILCE-7RM2 full-frame camera introduced on the 10 June 2015 features an Exmor R sensor as well.

Exmor RS is a stacked CMOS image sensor announced by Sony on 20 August 2012.

Fujifilm X-Pro1

The Fujifilm X-Pro1 is a mirrorless interchangeable-lens digital camera announced in January 2012 and launched in March 2012. It is part of Fujifilm's X-Series of cameras. In October 2012 Fujifilm has released a very similar, yet smaller, camera named the X-E1. In January 2016 Fujifilm announced its successor the X-Pro2.

Fujifilm X-T3

The Fujifilm X-T3 is a weather-resistant mirrorless interchangeable-lens camera announced on September 6, 2018. The X-T3 is the latest in the Fujifilm X Series lineup. It has a backside-illuminated X-Trans CMOS 4 APS-C sensor and an X-Processor 4 quad core processor. It is the successor to 2016's Fujifilm X-T2. It uses the Fujifilm X-mount.

The X-T3 is capable of recording video in 4K resolution up to 60 fps. The X-T3 is intended to be sold new either as the camera body only, or with the 18-55 mm lens. The camera is available in 2 colors, black and silver and is styled after an SLR camera.

Image sensor

An image sensor or imager is a sensor that detects and conveys information used to make an image. It does so by converting the variable attenuation of light waves (as they pass through or reflect off objects) into signals, small bursts of current that convey the information. The waves can be light or other electromagnetic radiation. Image sensors are used in electronic imaging devices of both analog and digital types, which include digital cameras, camera modules, medical imaging equipment, night vision equipment such as thermal imaging devices, radar, sonar, and others. As technology changes, digital imaging tends to replace analog imaging.

Early analog sensors for visible light were video camera tubes. Currently, used types are semiconductor charge-coupled devices (CCD) or active pixel sensors in complementary metal–oxide–semiconductor (CMOS) or N-type metal-oxide-semiconductor (NMOS, Live MOS) technologies. Analog sensors for invisible radiation tend to involve vacuum tubes of various kinds. Digital sensors include flat panel detectors.

In February 2018, researchers at Dartmouth College announced a new image sensing technology that the researchers call QIS, for Quanta Image Sensor. Instead of pixels, QIS chips have what the researchers call "jots." Each jot can detect a single particle of light, called a photon.

Inverter (logic gate)

In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. The truth table is shown on the right.

List of Sony Ericsson products

The following is a list of products manufactured under the Sony Ericsson brand. Most of the models have been released under multiple names, depending on region of release, currently usually indicated by a letter added to the end of the model number ('i' for international, 'a' for North America, and 'c' for mainland China), but indicated on some (mostly older) models by a slightly differing model number. Typically, there is one version for the European and US market, and another for the Asian market. However, some models have yet more versions.

Most "Walkman" branded models are also released as a non-Walkman version; such as the Sony Ericsson w580 and the s500. These versions usually differ only slightly.

Logic family

In computer engineering, a logic family may refer to one of two related concepts. A logic family of monolithic digital integrated circuit devices is a group of electronic logic gates constructed using one of several different designs, usually with compatible logic levels and power supply characteristics within a family. Many logic families were produced as individual components, each containing one or a few related basic logical functions, which could be used as "building-blocks" to create systems or as so-called "glue" to interconnect more complex integrated circuits.

A "logic family" may also refer to a set of techniques used to implement logic within VLSI integrated circuits such as central processors, memories, or other complex functions. Some such logic families use static techniques to minimize design complexity. Other such logic families, such as domino logic, use clocked dynamic techniques to minimize size, power consumption and delay.

Before the widespread use of integrated circuits, various solid-state and vacuum-tube logic systems were used but these were never as standardized and interoperable as the integrated-circuit devices.

NOR gate

The NOR gate is a digital logic gate that implements logical NOR - it behaves according to the truth table to the right. A HIGH output (1) results if both the inputs to the gate are LOW (0); if one or both input is HIGH (1), a LOW output (0) results. NOR is the result of the negation of the OR operator. It can also be seen as an AND gate with all the inputs inverted. NOR is a functionally complete operation—NOR gates can be combined to generate any other logical function. it shares this property with the NAND gate. By contrast, the OR operator is monotonic as it can only change LOW to HIGH but not vice versa.

In most, but not all, circuit implementations, the negation comes for free—including CMOS and TTL. In such logic families, OR is the more complicated operation; it may use a NOR followed by a NOT. A significant exception is some forms of the domino logic family.

The original Apollo Guidance Computer used 4,100 integrated circuits (IC), each one containing only a single 3-input NOR gate.

Nonvolatile BIOS memory

Nonvolatile BIOS memory refers to a small memory on PC motherboards that is used to store BIOS settings. It is traditionally called CMOS RAM because it uses a volatile, low-power complementary metal-oxide-semiconductor (CMOS) SRAM (such as the Motorola MC146818 or similar) powered by a small "CMOS" battery when system and standby power is off. The typical NVRAM capacity is 256 bytes.The CMOS RAM and the real-time clock have been integrated as a part of the southbridge chipset and it may not be a standalone chip on modern motherboards.

Sony Alpha 580

The Sony Alpha a580 (DSLR-A580) is a midrange-level digital single-lens reflex camera (DSLR) marketed by Sony and aimed at enthusiasts, it was released in August 2010. The camera features a 16.2 megapixel APS-C Type CMOS Exmor Sensor and features Sony's patented SteadyShot INSIDE stabilisation system which works with any attached lens.

Sony E-mount

The E-mount is a lens mount designed by Sony for their NEX ("New E-mount eXperience") and ILCE series of camcorders and mirrorless cameras. The E-mount supplements Sony's A-mount, allowing the company to develop more compact imaging devices while maintaining compatibility with 35mm sensors. E-mount achieves this by:

Minimizing mechanical complexity, removing mechanical aperture and focus drive.

Shortening the flange focal distance to 18 mm compared with earlier offerings from Sony which used 44.5 mm.

Reducing the radius of the flange.The short flange focal distance prohibits the use of an optical viewfinder as a mirror box mechanism cannot be included in this reduced distance. Therefore all E-mount cameras use an electronic viewfinder.

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