36-bit

In computer architecture, 36-bit integers, memory addresses, or other data units are those that are 36 bits (six six-bit characters) wide. Also, 36-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size.

Friden calculator - Ridai Museum of Modern Science, Tokyo - DSC07579
Friden mechanical calculator. The electronic computer word length of 36-bits was chosen, in part, to match its precision.

Prior to the introduction of computers, the state of the art in precision scientific and engineering calculation was the ten-digit, electrically powered, mechanical calculator, such as those manufactured by Friden, Marchant and Monroe. These calculators had a column of keys for each digit, and operators were trained to use all their fingers when entering numbers, so while some specialized calculators had more columns, ten was a practical limit. Computers, as the new competitor, had to match that accuracy. Decimal computers sold in that era, such as the IBM 650 and the IBM 7070, had a word length of ten digits, as did ENIAC, one of the earliest computers.

Early binary computers aimed at the same market therefore often used a 36-bit word length. This was long enough to represent positive and negative integers to an accuracy of ten decimal digits (35 bits would have been the minimum). It also allowed the storage of six alphanumeric characters encoded in a six-bit character code. Computers with 36-bit words included the MIT Lincoln Laboratory TX-2, the IBM 701/704/709/7090/7094, the UNIVAC 1103/1103A/1105 and 1100/2200 series, the General Electric GE-600/Honeywell 6000, the Digital Equipment Corporation PDP-6/PDP-10 (as used in the DECsystem-10/DECSYSTEM-20), and the Symbolics 3600 series.

Smaller machines like the PDP-1/PDP-9/PDP-15 used 18-bit words, so a double word was 36 bits.

These computers had addresses 12 to 18 bits in length. The addresses referred to 36-bit words, so the computers were limited to addressing between 4096 and 262144 words (24576 to 1572864 six-bit characters). The older 36-bit computers were limited to a similar amount of physical memory as well. Architectures that survived evolved over time to support larger virtual address spaces using memory segmentation or other mechanisms.

The common character packings included:

  • six 5.32-bit DEC Radix-50 characters, plus four spare bits
  • six 6-bit Fieldata or IBM BCD characters (ubiquitous in early usage)
  • six 6-bit ASCII characters, supporting the upper-case unaccented letters, digits, space, and most ASCII punctuation characters. It was used on the PDP-6 and PDP-10 under the name sixbit.
  • five 7-bit characters and 1 unused bit (the usual PDP-6/10 convention, called five-seven ASCII)[1][2]
  • four 8-bit characters (7-bit ASCII plus 1 spare bit, or 8-bit EBCDIC), plus four spare bits
  • four 9-bit characters[1][2] (the Multics convention).

Characters were extracted from words either using machine code shift and mask operations or with special-purpose hardware supporting 6-bit, 9-bit, or variable-length characters. The Univac 1100/2200 used the partial word designator of the instruction, the "J" field, to access characters. The GE-600 used special indirect words to access 6- and 9-bit characters. the PDP-6/10 had special instructions to access arbitrary-length byte fields.

The standard C programming language requires that the size of the char data type be at least 8 bits,[3] and that all data types other than bitfields have a size that is a multiple of the character size,[4] so standard C implementations on 36-bit machines would typically use 9-bit chars, although 12-bit, 18-bit, or 36-bit would also satisfy the requirements of the standard.[5]

By the time IBM introduced System/360 with 32-bit full words, scientific calculations had largely shifted to floating point, where double-precision formats offered more than 10-digit accuracy. The 360s also included instructions for variable length decimal arithmetic for commercial applications, so the practice of using word lengths that were a power of two quickly became commonplace, though at least one line of 36-bit computer systems are still sold as of 2019, the Unisys ClearPath Dorado series, which is the continuation of the UNIVAC 1100/2200 series of mainframe computers.

CompuServe was launched using 36-bit PDP-10 computers in the late 1960s. It continued using PDP-10 and DECSYSTEM-10-compatible hardware and retired the service in the late 2000s.

Other uses in electronics

The LatticeECP3 FPGAs from Lattice Semiconductor include multiplier slices that can be configured to support the multiplication of two 36-bit numbers.[6] The DSP block in Altera Stratix FPGAs can do 36-bit additions and multiplications.[7]

See also

References

  1. ^ a b Marshall Cline. "Would you please go over the rules about bytes, chars, and characters one more time?"
  2. ^ a b RFC 114: "A file transfer protocol"
  3. ^ ISO/IEC 9899:1999 specification. p. 20, § 5.2.4.2.1.
  4. ^ ISO/IEC 9899:1999 specification. p. 37, § 6.2.6.1 (4).
  5. ^ Marshall Cline. "C++ FAQ: the rules about bytes, chars, and characters".
  6. ^ "LatticeECP3 sysDSP Usage Guide" (PDF). Lattice Semiconductor. Retrieved December 27, 2013.
  7. ^ "Digital Signal Processing (DSP) Blocks in Stratix Devices". Altera+accessdate=December 27, 2013.
18-bit

In computer architecture, 18-bit integers, memory addresses, or other data units are those that are 18 bits (2.25 octets) wide. Also, 18-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size.

18 binary digits have 262144 (1000000 octal, 40000 hexadecimal) distinct combinations.

18 bits was a common word size for smaller computers in the 1960s, when large computers often used 36 bit words and 6-bit character sets were the norm.

DECSYSTEM-20

The DECSYSTEM-20 was a 36-bit Digital Equipment Corporation PDP-10 mainframe computer running the TOPS-20 operating system (products introduced in 1977).

PDP-10 computers running the TOPS-10 operating system were labeled DECsystem-10 as a way of differentiating them from the PDP-11. Later on, those systems running TOPS-20 (on the KL10 PDP-10 processors) were labeled DECSYSTEM-20 (the block capitals being the result of a lawsuit brought against DEC by Singer, which once made a computer called "system-10"). The DECSYSTEM-20 was sometimes called PDP-20, although this designation was never used by DEC.

The following models were produced:

DECSYSTEM-2020: bit-slice processor with up to 512 kilowords of solid state RAM (The ADP OnSite version of the DECSYSTEM-2020 supported 1 MW of RAM)

DECSYSTEM-2040: ECL processor with up to 1024 kilowords of magnetic core RAM

DECSYSTEM-2050: ECL processor with 2k words of cache and up to 1024 kilowords of RAM

DECSYSTEM-2060: ECL processor with 2k words of cache and up to 4096 kilowords of solid state memory

DECSYSTEM-2065: DECSYSTEM-2060 with MCA25 pager (double-sized (1024 entry) two-way associative hardware page table)The only significant difference the user could see between a DECsystem-10 and a DECSYSTEM-20 was the operating system and the color of the paint. Most (but not all) machines sold to run TOPS-10 were painted "Blasi Blue", whereas most TOPS-20 machines were painted "Terracotta" (often mistakenly called "Chinese Red" or orange; the actual name of the color on the paint cans was Terracotta).

There were some significant internal differences between the earlier KL10 Model A processors, used in the earlier DECsystem-10s running on KL10 processors, and the later KL10 Model Bs, used for the DECSYSTEM-20s. Model As used the original PDP-10 memory bus, with external memory modules. The later Model B processors used in the DECSYSTEM-20 used internal memory, mounted in the same cabinet as the CPU. The Model As also had different packaging; they came in the original tall PDP-10 cabinets, rather than the short ones used later on for the DECSYSTEM-20.

The last released implementation of DEC's 36-bit architecture was the single cabinet DECSYSTEM-2020, using a KS10 processor.

The DECSYSTEM-20 was primarily designed and used as a small mainframe for timesharing. That is, multiple users would concurrently log on to individual user accounts and share use of the main processor to compile and run applications. Separate disk allocations were maintained for all users by the operating system, and various levels of protection could be maintained by for System, Owner, Group, and World users. A model 2060, for example, could typically host up to 40 to 60 simultaneous users before exhibiting noticeably reduced response time.

DEC Radix-50

RADIX-50, commonly called Rad-50, RAD50 or DEC Squoze, is an uppercase only character encoding created by Digital Equipment Corporation for use on their DECsystem, PDP, and VAX computers. RADIX-50's 40-character repertoire (050 in octal) can encode six characters plus four additional bits into one 36-bit word (PDP-6, PDP-10/DECsystem-10, DECSYSTEM-20); three characters plus two additional bits into one 18-bit word (PDP-9, PDP-15); or three characters into one 16-bit word (PDP-11, VAX).

The actual encoding differed between the 36-bit and 16-bit systems.

GE-600 series

The GE-600 series was a family of 36-bit mainframe computers originating in the 1960s, built by General Electric (GE). When GE left the mainframe business the line was sold to Honeywell, which built similar systems into the 1990s as the division moved to Groupe Bull and then NEC.

The system is perhaps best known as the platform on which the Dartmouth Time Sharing System (DTSS) spent most of its life, and the base machine for the Multics operating system as well. Multics was supported by virtual memory additions made to later versions of the series.

General Comprehensive Operating System

General Comprehensive Operating System (GCOS, ; originally GECOS, General Electric Comprehensive Operating Supervisor) is a family of operating systems oriented toward the 36-bit GE/Honeywell mainframe computers.The original version of GCOS was developed by General Electric from 1962. The operating system is still used today in its most recent versions (GCOS 7 and GCOS 8) on servers and mainframes produced by Groupe Bull, primarily through emulation, to provide continuity with legacy mainframe environments. Note that GCOS 7 and GCOS 8 are separate branches of the operating system and continue to be developed alongside each other.

IBM 700/7000 series

The IBM 700/7000 series is a series of large-scale (mainframe) computer systems that were made by IBM through the 1950s and early 1960s. The series includes several different, incompatible processor architectures. The 700s use vacuum tube logic and were made obsolete by the introduction of the transistorized 7000s. The 7000s, in turn, were eventually replaced with System/360, which was announced in 1964. However the 360/65, the first 360 powerful enough to replace 7000s, did not become available until November 1965. Early problems with OS/360 and the high cost of converting software kept many 7000s in service for years afterward.

IBM 704

The IBM 704, introduced by IBM in 1954, is the first mass-produced computer with floating-point arithmetic hardware. The IBM 704 Manual of operation states:

The type 704 Electronic Data-Processing Machine is a large-scale, high-speed electronic calculator controlled by an internally stored program of the single address type.

The 704 at that time was thus regarded as "pretty much the only computer that could handle complex math." The 704 was a significant improvement over the earlier IBM 701 in terms of architecture and implementation. Like the 701, the 704 uses vacuum tube logic circuitry and 36-bit binary words. Changes from the 701 include the use of core memory instead of Williams tubes, floating-point arithmetic instructions, 15-bit addressing and the addition of three index registers. To support these new features, the instructions were expanded to use the full 36-bit word. The new instruction set, which is not compatible with the 701, became the base for the "scientific architecture" subclass of the IBM 700/7000 series computers.

The 704 can execute up to 12,000 floating-point additions per second. IBM sold 140 type 704 systems between 1955 and 1960.

IBM 709

The IBM 709 was a computer system, initially announced by IBM in January 1957 and first installed during August 1958. The 709 was an improved version of its predecessor, the IBM 704, and was the second iteration of the IBM 700/7000 series of scientific computers. The improvements included overlapped input/output, indirect addressing, and three "convert" instructions which provided support for decimal arithmetic, leading zero suppression, and several other operations. The 709 had 32,768 words of 36-bit magnetic core memory and could execute 42,000 add or subtract instructions per second. It could multiply two 36-bit integers at a rate of 5000 per second.An optional hardware emulator executed legacy IBM 704 programs on the IBM 709. This was the first commercially available emulator. Registers and most 704 instructions were emulated in 709 hardware. Complex 704 instructions such as floating point trap and input-output routines were emulated in 709 software.

The FORTRAN Assembly Program was first introduced for the 709.

It was a large system; customer installations used 100 to 250 kW to run them and almost as much again on the cooling. It weighed about 2,110 pounds (960 kg) (without peripheral equipment).

The 709 was built using vacuum tubes.

IBM introduced a transistorized version of the 709, called the IBM 7090, in November 1959.

IBM 7090

The IBM 7090 is a second-generation transistorized version of the earlier IBM 709 vacuum tube mainframe computer that was designed for "large-scale scientific and technological applications". The 7090 is the third member of the IBM 700/7000 series scientific computers. The first 7090 installation was in November 1959. In 1960, a typical system sold for $2.9 million (equivalent to $18 million in 2018) or could be rented for $63,500 a month (equivalent to $405,000 in 2016).

The 7090 uses a 36-bit word length, with an address space of 32,768 words (15-bit addresses). It operates with a basic memory cycle of 2.18 μs, using the IBM 7302 Core Storage core memory technology from the IBM 7030 (Stretch) project.

With a processing speed of around 100 Kflop/s, the 7090 is six times faster than the 709, and could be rented for half the price.

MBus (SPARC)

MBus is a computer bus designed and implemented by Sun Microsystems for communication between high speed computer system components, such as the central processing unit, motherboard and main memory. Contrast this with SBus, used in the same machines to connect add-on cards to the motherboard.

MBus was first used in Sun's first multiprocessor SPARC-based system, the SPARCserver 600MP series (launched in 1991), and later found use in the SPARCstation 10 and SPARCstation 20 workstations. The bus permitted the integration of several microprocessors on a single motherboard, in a multiprocessing configuration with up to eight CPUs packaged in detachable MBus modules. However, in practice, the number of processors per MBus was limited to four. Single processor systems were also sold that used the MBus protocol internally, but with the CPUs permanently attached to the motherboard to lower manufacturing costs.

MBus specified a 64-bit datapath, which used 36-bit physical addressing, giving an address space of 64 GB. The transfer rate is 80 MB/s sustained (320 MB/s peak) at 40 MHz, or 100 MB/s (400 MB/s peak) at 50 MHz. Bus controlling is done by an arbiter. Interrupt, reset, and timeout logic are also specified.

Memory address

In computing, a memory address is a reference to a specific memory location used at various levels by software and hardware. Memory addresses are fixed-length sequences of digits conventionally displayed and manipulated as unsigned integers. Such numerical semantic bases itself upon features of CPU (such as the instruction pointer and incremental address registers), as well upon use of the memory like an array endorsed by various programming languages.

PDP-10

Digital Equipment Corporation's PDP-10, later marketed as the DECsystem-10, was a mainframe computer family manufactured beginning in 1966; it was discontinued in 1983. 1970s models and beyond were marketed under the DECsystem-10 name, especially as the TOPS-10 operating system became widely used.The PDP-10's architecture is almost identical to that of DEC's earlier PDP-6, sharing the same 36-bit word length and slightly extending the instruction set (but with improved hardware implementation). Some aspects of the instruction set are unusual, most notably the byte instructions, which operated on bit fields of any size from 1 to 36 bits inclusive, according to the general definition of a byte as a contiguous sequence of a fixed number of bits.

The PDP-10 is the machine that made time-sharing common, and this and other features made it a common fixture in many university computing facilities and research labs during the 1970s, the most notable being Harvard University's Aiken Lab, MIT's AI Lab and Project MAC, Stanford's SAIL, Computer Center Corporation (CCC), ETH (ZIR), and Carnegie Mellon University. Its main operating systems, TOPS-10 and TENEX, were used to build out the early ARPANET. For these reasons, the PDP-10 looms large in early hacker folklore.

Projects to extend the PDP-10 line were eclipsed by the success of the unrelated VAX superminicomputer, and the cancellation of the PDP-10 line was announced in 1983.

PDP-6

The PDP-6 (Programmed Data Processor-6) was a computer model developed by Digital Equipment Corporation (DEC) in 1964. It was influential primarily as the prototype (effectively) for the later PDP-10; the instruction sets of the two machines are almost identical.

S-1 Lisp

S-1 Lisp was an Lisp implementation written in Lisp for the 36-bit pipelined S-1 Mark IIA supercomputer computer architecture, which has 32 megawords of RAM.

TOPS-20

The TOPS-20 operating system by Digital Equipment Corporation (DEC) was a proprietary OS used on some of DEC's 36-bit

mainframe computers. The Hardware Reference Manual was described as for "DECsystem-10/DECSYSTEM-20 Processor" (meaning

the DEC PDP-10 and the DECSYSTEM-20).TOPS-20 began in 1969 as the TENEX operating system of Bolt, Beranek and Newman (BBN) and shipped as a product by DEC starting in 1976. TOPS-20 is almost entirely unrelated to the similarly named TOPS-10, but it was shipped with the PA1050 TOPS-10 Monitor Calls emulation facility which allowed most, but not all, TOPS-10 executables to run unchanged. As a matter of policy, DEC did not update PA1050 to support later TOPS-10 additions except where required by DEC software.

TOPS-20 competed with TOPS-10, ITS and WAITS—all available for the PDP-10

(all of which were notable time-sharing systems) during this timeframe.

UNIVAC 1100/2200 series

The UNIVAC 1100/2200 series is a series of compatible 36-bit computer systems, beginning with the UNIVAC 1107 in 1962, initially made by Sperry Rand. The series continues to be supported today by Unisys Corporation as the ClearPath Dorado Series. The solid-state 1107 model number was in the same sequence as the earlier vacuum-tube computers, but the early computers were not compatible with the solid-state successors.

UNIVAC 1103

The UNIVAC 1103 or ERA 1103, a successor to the UNIVAC 1101, was a computer system designed by Engineering Research Associates and built by the Remington Rand corporation in October 1953. It was the first computer for which Seymour Cray was credited with design work.

UNIVAC FASTRAND

FASTRAND was a magnetic drum mass storage system built by Sperry Rand Corporation (later Sperry Univac) for their UNIVAC 1100 series and 418/490/494 series computers. A FASTRAND subsystem consisted of one or two Control Units and up to eight FASTRAND units. A dual-access FASTRAND subsystem included two complete control units, and provided parallel data paths that allowed simultaneous operations on any two FASTRAND units in the subsystem. Each control unit interfaced to one (optionally two) 1100 Series (36-bit), or 490 Series (30-bit), parallel I/O channels.

A voice coil actuator moved a bar containing multiple single track recording heads, so these drums operated much like moving head disk drives with multiple disks. The heads "flew" on self-acting hydrodynamic air bearings. The drums had a plated magnetic recording surface. An optional feature called Fastband included 24 additional tracks with fixed read/write heads. This feature provided rapid access (35 ms. average access time), and a write lockout feature.

The Fastrands were very heavy (5,000 pounds) and large, approximately 8' long. Due to their weight, FASTRAND units were usually not installed on "false floor", and required special rigging and mounts to move and/or install. There were reported cases of drum bearing failures that caused the machine to tear itself apart and send the heavy drum crashing through walls.

At the time of their introduction the storage capacity exceeded any other random access mass storage disk or drum.

There were three models of FASTRAND drives:

FASTRAND I had a single drum. The large mass of the rotating drum caused gyroscopic precession of the unit, making it tend to spin on the computer room floor as the Earth rotated under it. Very few of these devices were delivered.

FASTRAND II (the majority of units produced) had two counter-rotating drums to eliminate the gyroscopic effect. One actuator bar with heads was located between the drums.

FASTRAND III, introduced in 1970, was physically identical to the FASTRAND II, but increased the recording density by 50%.

Word (computer architecture)

In computing, a word is the natural unit of data used by a particular processor design. A word is a fixed-sized piece of data handled as a unit by the instruction set or the hardware of the processor. The number of bits in a word (the word size, word width, or word length) is an important characteristic of any specific processor design or computer architecture.

The size of a word is reflected in many aspects of a computer's structure and operation; the majority of the registers in a processor are usually word sized and the largest piece of data that can be transferred to and from the working memory in a single operation is a word in many (not all) architectures. The largest possible address size, used to designate a location in memory, is typically a hardware word (here, "hardware word" means the full-sized natural word of the processor, as opposed to any other definition used).

Modern processors, including those in embedded systems, usually have a word size of 8, 16, 24, 32, or 64 bits; those in modern general-purpose computers in particular usually use 32 or 64 bits. Special-purpose digital processors, such as DSPs for instance, may use other sizes, and many other sizes have been used historically, including 9, 12, 18, 24, 26, 36, 39, 40, 48, and 60 bits. Several of the earliest computers (and a few modern as well) used binary-coded decimal rather than plain binary, typically having a word size of 10 or 12 decimal digits, and some early decimal computers had no fixed word length at all.

The size of a word can sometimes differ from the expected due to backward compatibility with earlier computers. If multiple compatible variations or a family of processors share a common architecture and instruction set but differ in their word sizes, their documentation and software may become notationally complex to accommodate the difference (see Size families below).

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