128-bit

In computer architecture, 128-bit integers, memory addresses, or other data units are those that are 128 bits (16 octets) wide. Also, 128-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size.

While there are currently no mainstream general-purpose processors built to operate on 128-bit integers or addresses, a number of processors do have specialized ways to operate on 128-bit chunks of data. The IBM System/370 could be considered the first simple 128-bit computer, as it used 128-bit floating-point registers. Most modern CPUs feature single-instruction multiple-data (SIMD) instruction sets (Streaming SIMD Extensions, AltiVec etc.) where 128-bit vector registers are used to store several smaller numbers, such as four 32-bit floating-point numbers. A single instruction can then operate on all these values in parallel. However, these processors do not operate on individual numbers that are 128 binary digits in length; only their registers have the size of 128 bits.

The DEC VAX supported operations on 128-bit integer ('O' or octaword) and 128-bit floating-point ('H-float' or HFLOAT) datatypes. Support for such operations was an upgrade option rather than being a standard feature. Since the VAXX's registers were 32 bits wide, a 128-bit operation used four consecutive registers or four longwords in memory.

The ICL 2900 Series provided a 128-bit accumulator, and its instruction set included 128-bit floating-point and packed decimal arithmetic.

In the same way that compilers emulate e.g. 64-bit integer arithmetic on architectures with register sizes less than 64 bits, some compilers also support 128-bit integer arithmetic. For example, the GCC C compiler 4.6 and later has a 128-bit integer type __int128 for some architectures.[1] For the C programming language, this is a compiler-specific extension, as C11 itself does not guarantee support for 128-bit integers.

A 128-bit register can store 2128 (over 3.40 × 1038) different values. The range of integer values that can be stored in 128 bits depends on the integer representation used. With the two most common representations, the range is 0 through 340,282,366,920,938,463,463,374,607,431,768,211,455 (2128 − 1) for representation as an (unsigned) binary number, and −170,141,183,460,469,231,731,687,303,715,884,105,728 (−2127) through 170,141,183,460,469,231,731,687,303,715,884,105,727 (2127 − 1) for representation as two's complement.

Uses

  • The free software used to implement RISC-V architecture is defined for 32, 64 and 128 bits of integer data width.
  • Universally Unique Identifiers (UUID) consist of a 128-bit value.
  • IPv6 routes computer network traffic amongst a 128-bit range of addresses.
  • ZFS is a 128-bit file system.
  • GPU chips commonly move data across a 128-bit bus.[2]
  • 128 bits is a common key size for symmetric ciphers and a common block size for block ciphers in cryptography.
  • 128-bit processors could be used for addressing directly up to 2128 (over 3.40×1038) bytes, which would greatly exceed the total data stored on Earth as of 2010, which has been estimated to be around 1.2 zettabytes (1.42×1021 bytes).[3]
  • Quadruple precision (128-bit) floating-point numbers can store 64-bit fixed point numbers or integers accurately without losing precision.
  • Decimal128 floating-point numbers can represent numbers with up to 34 significant digits.
  • The AS/400 virtual instruction set defines all pointers as 128-bit. This gets translated to the hardware's real instruction set as required, allowing the underlying hardware to change without needing to recompile the software. Past hardware was 48-bit CISC, while current hardware is 64-bit PowerPC. Because pointers are defined to be 128-bit, future hardware may be 128-bit without software incompatibility.
  • Increasing the word size can speed up multiple precision mathematical libraries, with applications to cryptography, and potentially speed up algorithms used in complex mathematical processing (numerical analysis, signal processing, complex photo editing and audio and video processing).
  • MD5 is a widely used hash function producing a 128-bit hash value.
  • Apache Avro uses a 128-bit random number as synchronization marker for efficient splitting of data files.[4][5]

History

A 128-bit multicomparator was described by researchers in 1976.[6]

A CPU with 128-bit multimedia extensions was designed by researchers in 1999.[7]

References

  1. ^ "GCC 4.6 Release Series - Changes, New Features, and Fixes". Retrieved 25 July 2016.
  2. ^ Woligroski, Don (24 July 2006). "The Graphics Processor". Tom's Hardware. Archived from the original on 11 April 2013. Retrieved 24 February 2013.
  3. ^ Miller, Rich (4 May 2010). "Digital Universe nears a Zettabyte". Data Center Knowledge. Archived from the original on 6 May 2010. Retrieved 16 September 2010.
  4. ^ Kleppmann, Martin (24 January 2013). "Re: Synchronization Markers". Archived from the original on 27 September 2015.
  5. ^ "Apache Avro 1.8.0 Specification". Apache Software Foundation.
  6. ^ Mead, Carver A.; Pashley, Richard D.; Britton, Lee D.; Daimon, Yoshiaki T.; Sando, Stewart F., Jr. (October 1976). "128-Bit Multicomparator" (PDF). IEEE Journal of Solid-State Circuits. 11 (5): 692–695. doi:10.1109/JSSC.1976.1050799. Archived (PDF) from the original on 3 November 2018.
  7. ^ Suzuoki, M.; Kutaragi, K.; Hiroi, T.; Magoshi, H.; Okamoto, S.; Oka, M.; Ohba, A.; Yamamoto, Y.; Furuhashi, M.; Tanaka, M.; Yutaka, T.; Okada, T.; Nagamatsu, M.; Urakawa, Y.; Funyu, M.; Kunimatsu, A.; Goto, H.; Hashimoto, K.; Ide, N.; Murakami, H.; Ohtaguro, Y.; Aono, A. (November 1999). "A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder". IEEE Journal of Solid-State Circuits. 34 (11): 1608–1618. doi:10.1109/4.799870.
256-bit

In computer architecture, 256-bit integers, memory addresses, or other data units are those that are 256 bits (32 octets) wide. Also, 256-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size.

There are currently no mainstream general-purpose processors built to operate on 256-bit integers or addresses, though a number of processors do operate on 256-bit data. CPUs feature SIMD instruction sets (Advanced Vector Extensions and the FMA instruction set etc.) where 256-bit vector registers are used to store several smaller numbers, such as eight 32-bit floating-point numbers, and a single instruction can operate on all these values in parallel. However, these processors do not operate on individual numbers that are 256 binary digits in length, only their registers have the size of 256-bits. Binary digits are found together in 128-bit collections.

Advanced Vector Extensions

Advanced Vector Extensions (AVX, also known as Sandy Bridge New Extensions) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge processor shipping in Q1 2011 and later on by AMD with the Bulldozer processor shipping in Q3 2011. AVX provides new features, new instructions and a new coding scheme.

AVX2 expands most integer commands to 256 bits and introduces fused multiply-accumulate (FMA) operations. AVX-512 expands AVX to 512-bit support using a new EVEX prefix encoding proposed by Intel in July 2013 and first supported by Intel with the Knights Landing processor, which shipped in 2016.

CRYPTREC

CRYPTREC is the Cryptography Research and Evaluation Committees set up by the Japanese Government to evaluate and recommend cryptographic techniques for government and industrial use. It is comparable in many respects to the European Union's NESSIE project and to the Advanced Encryption Standard process run by NIST in the U.S..

Graphics processing unit

A graphics processing unit (GPU) is a specialized electronic circuit designed to rapidly manipulate and alter memory to accelerate the creation of images in a frame buffer intended for output to a display device. GPUs are used in embedded systems, mobile phones, personal computers, workstations, and game consoles. Modern GPUs are very efficient at manipulating computer graphics and image processing. Their highly parallel structure makes them more efficient than general-purpose central processing units (CPUs) for algorithms that process large blocks of data in parallel. In a personal computer, a GPU can be present on a video card or embedded on the motherboard. In certain CPUs, they are embedded on the CPU die.The term GPU has been used from at least the 1980s. It was popularized by Nvidia in 1999, who marketed the GeForce 256 as "the world's first GPU". It was presented as a "single-chip processor with integrated transform, lighting, triangle setup/clipping, and rendering engines". Rival ATI Technologies coined the term "visual processing unit" or VPU with the release of the Radeon 9700 in 2002.

Key size

In cryptography, key size or key length is the number of bits in a key used by a cryptographic algorithm (such as a cipher).

Key length defines the upper-bound on an algorithm's security (i.e., a logarithmic measure of the fastest known attack against an algorithm, relative to the key length), since the security of all algorithms can be violated by brute-force attacks. Ideally, key length would coincide with the lower-bound on an algorithm's security. Indeed, most symmetric-key algorithms are designed to have security equal to their key length. However, after design, a new attack might be discovered. For instance, Triple DES was designed to have a 168 bit key, but an attack of complexity 2112 is now known (i.e., Triple DES has 112 bits of security). Nevertheless, as long as the relation between key length and security is sufficient for a particular application, then it doesn't matter if key length and security coincide. This is important for asymmetric-key algorithms, because no such algorithm is known to satisfy this property; elliptic curve cryptography comes the closest with an effective security of roughly half its key length.

List of AMD Turion microprocessors

Turion 64 is the name of a family of CPUs designed by AMD for the mobile computing market.

List of AMD graphics processing units

The following is a list that contains general information about GPUs and video cards by Advanced Micro Devices (AMD), including those by ATI Technologies before 2006, based on official specifications in table form.

List of home video game consoles

This is a list of home video game consoles in chronological order, which includes the very first home video game consoles ever created, such as first generation Pong consoles, from the first ever cartridge console Odyssey, ranging from the major video game companies such as Magnavox, Atari, Nintendo, Sega, NEC, 3DO, SNK, Sony, Microsoft to secondary market consoles.

The list is divided into eras which are named based on the dominant console type of the era, though not all consoles of those eras are of the same type. Some eras are referred to based on how many bits a major console could process. The "128-bit era" (sixth generation) was the final era in which this practice was widespread.This list does not include other types of video game consoles such as handheld game consoles, which are usually of lower computational power than home consoles due to their smaller size, microconsoles, which are usually low-cost Android-based devices that rely on downloading, or dedicated consoles past the First Generation, which have games built in and do not use any form of physical media. Consoles have been redesigned from time to time to improve their market appeal. Redesigned models are not listed on their own.

MUGI

In cryptography, MUGI is a pseudorandom number generator (PRNG) designed for use as a stream cipher. It was among the cryptographic techniques recommended for Japanese government use by CRYPTREC in 2003, however, has been dropped to "candidate" by CRYPTREC revision in 2013.

MUGI takes a 128-bit secret key and a 128-bit initial vector (IV). After a key- and IV- setup process, MUGI outputs 64-bit output strings based on the internal state, while updating the internal state after each output block. MUGI has a 1216-bit internal state; there are three 64-bit registers (the "state") and 16 64-bit registers (the "buffer").

MUGI uses the non-linear S-box that was originally defined in Advanced Encryption Standard (AES). A part of the linear transformation also reuses the MDS matrix of AES. The basic design is influenced by that of Panama.

Mercy (cipher)

In cryptography, Mercy is a tweakable block cipher designed by Paul Crowley for disk encryption.

The block size is 4096 bits—unusually large for a block cipher, but a standard disk sector size. Mercy uses a 128-bit secret key, along with a 128-bit non-secret tweak for each block. In disk encryption, the sector number would be used as a tweak. Mercy uses a 6-round Feistel network structure with partial key whitening. The round function uses a key-dependent state machine which borrows some structure from the stream cipher WAKE, with key-dependent S-boxes based on the Nyberg S-boxes also used in AES.

Scott Fluhrer has discovered a differential attack that works against the full 6 rounds of Mercy. This attack can even be extended to a seven-round variant.

N-Hash

In cryptography, N-Hash is a cryptographic hash function based on the FEAL round function, and is now considered insecure. It was proposed in 1990 by Miyaguchi et al.; weaknesses were published the following year.

N-Hash has a 128-bit hash size. A message is divided into 128-bit blocks, and each block is combined with the hash value computed so far using the g compression function. g contains eight rounds, each of which uses an F function, similar to the one used by FEAL.

Eli Biham and Adi Shamir (1991) applied the technique of differential cryptanalysis to N-Hash, and showed that collisions could be generated faster than by a birthday attack for N-Hash variants with even up to 12 rounds.

Nvidia Quadro

Quadro is Nvidia's brand for graphics cards intended for use in workstations running professional computer-aided design (CAD), computer-generated imagery (CGI), digital content creation (DCC) applications, scientific calculations and machine learning.

The GPU chips on Quadro-branded graphics cards are identical to those used on GeForce-branded graphics cards. The Quadro cards differ substantially in their ECC memory and enhanced floating point precision, which tremendously reduce the risks of calculation errors.

The Nvidia Quadro product line directly competes with AMD's Radeon Pro line of professional workstation cards.

Outline of cryptography

The following outline is provided as an overview of and topical guide to cryptography:

Cryptography (or cryptology) – practice and study of hiding information. Modern cryptography intersects the disciplines of mathematics, computer science, and engineering. Applications of cryptography include ATM cards, computer passwords, and electronic commerce.

Power ISA

The Power ISA is an instruction set architecture (ISA) developed by the OpenPOWER Foundation, led by IBM. It was originally developed by the now defunct Power.org industry group. Power ISA is an evolution of the PowerPC ISA, created by the mergers of the core PowerPC ISA and the optional Book E for embedded applications. The merger of these two components in 2006 was led by Power.org founders IBM and Freescale Semiconductor. The ISA is divided into several categories and every component is defined as a part of a category; each category resides within a certain Book. Processors implement a set of these categories. Different classes of processors are required to implement certain categories, for example a server class processor includes the categories Base, Server, Floating-Point, 64-Bit, etc. All processors implement the Base category.

The Power ISA is a RISC load/store architecture. It has multiple sets of registers:

thirty-two 32-bit or 64-bit general purpose registers (GPRs) for integer operations.

sixty-four 128-bit vector scalar registers (VSRs) for vector operations and floating point operations.

thirty-two 64-bit floating-point registers (FPRs) as part of the VSRs for floating point operations.

thirty-two 128-bit vector registers (VRs) as part of the VSRs for vector operations.

Eight 4-bit condition register fields (CRs) for comparison and control flow.

Special registers: counter register (CTR), link register (LR), time base (TBU, TBL), alternate time base (ATBU, ATBL), accumulator (ACC), status registers (XER, FPSCR, VSCR, SPEFSCR).Instructions have a length of 32 bits, with the exception of the VLE (variable-length encoding) subset that provides for higher code density for low-end embedded applications. Most instructions are triadic, i.e. have two source operands and one destination. Single and double precision IEEE-754 compliant floating point operations are supported, including additional fused multiply–add (FMA) and decimal floating-point instructions. There are provisions for SIMD operations on integer and floating point data on up to 16 elements in a single instruction.

Support for Harvard cache, i.e. split data and instruction caches, as well as support for unified caches. Memory operations are strictly load/store, but allow for out-of-order execution. Support for both big and little-endian addressing with separate categories for moded and per-page endianness. Support for both 32-bit and 64-bit addressing.

Different modes of operation include user, supervisor and hypervisor.

Quadruple-precision floating-point format

In computing, quadruple precision (or quad precision) is a binary floating point–based computer number format that occupies 16 bytes (128 bits) with precision more than twice the 53-bit double precision.

This 128-bit quadruple precision is designed not only for applications requiring results in higher than double precision, but also, as a primary function, to allow the computation of double precision results more reliably and accurately by minimising overflow and round-off errors in intermediate calculations and scratch variables. William Kahan, primary architect of the original IEEE-754 floating point standard noted, "For now the 10-byte Extended format is a tolerable compromise between the value of extra-precise arithmetic and the price of implementing it to run fast; very soon two more bytes of precision will become tolerable, and ultimately a 16-byte format ... That kind of gradual evolution towards wider precision was already in view when IEEE Standard 754 for Floating-Point Arithmetic was framed."In IEEE 754-2008 the 128-bit base-2 format is officially referred to as binary128.

Radeon HD 7000 Series

The Radeon HD 7000 series, codenamed "Southern Islands", is a family of GPUs developed by AMD, and manufactured on TSMC's 28 nm process. The primary competitor of Southern Islands, Nvidia's GeForce 600 Series (also manufactured at TSMC), also shipped during Q1 2012, largely due to the immaturity of the 28 nm process.

Sixth generation of video game consoles

In the history of video games, the sixth-generation era (sometimes called the 128-bit era; see "bits and system power" below) refers to the computer and video games, video game consoles, and handheld gaming devices available at the turn of the 21st century, starting in 1998. Platforms in the sixth generation include consoles from four companies: the Sega Dreamcast (DC), Sony PlayStation 2 (PS2), Nintendo GameCube (GC), and Microsoft Xbox. This era began on November 27, 1998, with the Japanese release of the Dreamcast, which was joined by the PlayStation 2 in March 2000, and the GameCube and Xbox in 2001. The Dreamcast was the first to be discontinued, in 2001. The GameCube was next, in 2007, the Xbox in 2009, and the PlayStation 2 in 2013. Meanwhile, the seventh generation of consoles started in November 2005 with the launch of the Xbox 360.Bit ratings (i.e. "64-bit" or "32-bit" for the previous generation) for most consoles largely fell by the wayside during this era, with the notable exceptions being promotions for the Dreamcast and PS2 that advertised "128-bit graphics" at the start of the generation. The number of "bits" cited in this way in console names refers to the CPU word size, and had been used by hardware marketing departments as a "show of power" for many years. However, there is little to be gained from increasing the word size much beyond 32 or 64 bits because, once this level is reached, performance depends on more varied factors, such as processor clock speed, bandwidth, and memory size.The sixth generation of handhelds began with the release of the Neo Geo Pocket Color by SNK in 1998 and Bandai's WonderSwan Color, launched in Japan in 1999. Nintendo maintained its dominant share of the handheld market with the release in 2001 of the Game Boy Advance, which featured many upgrades and new features over the Game Boy. The Game Boy Advance was discontinued around in early 2010. The next generation of handheld consoles began in November 2004, with the North American introduction of the Nintendo DS.

The last official Dreamcast games were released in 2002 (North America and Europe) and 2007 (Japan). The last GameCube games were released in 2006 (Japan) and 2007 (North America and Europe). The last Xbox games were released in 2007 (Japan) and 2008 (Europe and North America). Pro Evolution Soccer 2014 was the last game for the PlayStation 2 (in Europe), which was released in November 2013. The last PS2 game, Final Fantasy XI: Rhapsodies of Vana'diel, was released in May 2015, marking the end of this generation.

Square (cipher)

In cryptography, Square (sometimes written SQUARE) is a block cipher invented by Joan Daemen and Vincent Rijmen. The design, published in 1997, is a forerunner to Rijndael, which has been adopted as the Advanced Encryption Standard. Square was introduced together with a new form of cryptanalysis discovered by Lars Knudsen, called the "Square attack".

The structure of Square is a substitution–permutation network with eight rounds, operating on 128-bit blocks and using a 128-bit key.

Square is not patented.

Syskey

The SAM Lock Tool, better known as Syskey (the name of its executable file) is a discontinued component of Windows NT that encrypts the Security Account Manager (SAM) database using a 128-bit RC4 encryption key.First introduced on Windows NT 4.0 SP3, it was removed on Windows 10 and Windows Server 2016, due to its use of cryptography considered insecure by modern standards, and its use as part of scams as a form of ransomware. Microsoft officially recommended use of BitLocker disk encryption as an alternative.

Models
Architecture
Instruction set
architectures
Execution
Parallelism
Processor
performance
Types
Word size
Core count
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management
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